The steps required to perform the HDL instantiation flow are:
- Customize and generate the ILA and/or VIO debug cores that have the right number of probe ports for the signals you want to probe.
- (Optional) Customize and generate the JTAG-to-AXI Master debug core and connect it to an AXI slave interface of an AXI peripheral or interconnect core in your design.
- Synthesize the design containing the debug cores.
- (Optional) Modify debug hub core properties.
- Implement the design containing the debug cores.