The System ILA IP in the IP integrator Block Design must be instantiated. The figure below is a snapshot of the Block Design with two debug cores instantiated in the design, the System ILA, and the JTAG to AXI Master IP cores.
After this Block Design has been validated and synthesized, you can open the Debug window in the synthesized design to view the debug cores instantiated and inserted into the design. The System ILA and JTAG to AXI Master debug cores are displayed as shown below.
For more details on how these interfaces can be used for debug in the Hardware Manager and to take advantage of the AXI Event level debug, see Debugging AXI Interfaces in the Hardware Manager.