If the JTAG Clock is inactive or unavailable, you will not be able to connect to the hardware target.
If the Debug Hub Clock is inactive or unavailable, the Vivado® Hardware Manager issues the following error message:
INFO: [Labtools 27-1434] Device xxx (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
If any of the Debug Core Clocks are inactive or unavailable, the Vivado Hardware Manager issues the following error message:
INFO: [Labtools 27-2302] Device xxx (JTAG device index = 1) is programmed with a design that has 1 ILA core(s). CRITICAL WARNING: [Labtools 27-1433] Device xxx (JTAG device index = 1) is programmed with a design that has an unrecognizable debug core (slave type = 17) at user chain = 1, index = 0. Resolution: 1) Ensure that the clock signal connected to the debug core and/or debug hub is clean and free-running. 2) Ensure that the clock connected to the debug core and/or debug hub meets all timing constraints. 3) Ensure that the clock connected to debug core and/or debug hub is faster than the JTAG clock frequency.
The following figure is an example of a design with two ILA cores:
The example design contains two ILA cores, ILA "A" and ILA"B."
The clocking topology of this debug network is as follows. After the design has been programmed into the device, the Vivado Hardware Manager tries to discover the existence of the Debug Hub core in the design. The Debug Hub in turn tries to discover and account for all the debug cores connected to it. In this design the debug cores are ILA "A" and ILA "B." Notice that CLKA drives both the ILA "A" and the Debug Hub core. CLKB drives the ILA "B" debug core.
When you connect to the target and program the device, expect an active JTAG clk. In the Debug Core Discovery Phase, expect a free running and stable clock driving the Debug Hub core, which in this case is CLKA. During Debug Core Measurement phase (i.e., anything that involves getting/setting properties on the debug core), expect an active JTAG, Debug Hub, and Debug Core clocks. If you expect to trigger and capture data on ILA "B", expect free running and stable JTAG, Debug Hub (CLKA), and Debug Core (CLKB) Clocks.