With the Reset After Reconfiguration feature, the reconfiguring region is held in a steady state during partial reconfiguration, and then all logic in the new RM is initialized to its starting values. Static routes can still freely pass unaffected through the region, and static logic (and all other dynamic regions) elsewhere in the device continue to operate normally during partial reconfiguration. Dynamic Function eXchange with this feature behaves in the same manner as the initial configuration of the FPGA, with synchronous elements being released in a known, initialized state.
This is the
set_property RESET_AFTER_RECONFIG true [get_pblocks <reconfig_pblock_name>]
If the design uses the DRP interface of the 7 series XADC component, the interface will be blocked (held in reset) during partial reconfiguration when RESET_AFTER_RECONFIG is enabled. The interface will be non-responsive (busy), and there will be no access during the length of the reconfiguration period. The interface will become accessible again after partial reconfiguration is complete.
To apply the Reset After Reconfiguration methodology for 7 series and Zynq 7000 SoC devices, Pblock constraints must align to reconfigurable
frames. Because the GSR affects every synchronous element within the region, exclusive
use of reconfiguration frames is required; static logic is not permitted within these
reconfigurable frames (static routing is permitted). Pblocks must align vertically to
clock regions, because that matches the base region for a reconfigurable frame. The
width of a Pblock does not matter when using
UltraScale™ and UltraScale+™ devices do not have this clock region
alignment requirement, and GSR can be applied at a fine granularity. Because of this,
RESET_AFTER_RECONFIG is automatically applied for
all RPs in the UltraScale™ and UltraScale+ architecture. This capability cannot be
In the following figure, the Pblock on the left (
pblock_shift) is frame-aligned because the top and bottom of the Pblock
align to the height of clock region X1Y3. The Pblock on the right (
pblock_count) is not frame-aligned.
- For 7 series devices: Pblocks
that are not frame-aligned (such as
pblock_countin the figure below) cannot have
RESET_AFTER_RECONFIGset because any static logic placed between it and the clock region boundary above it would be affected by GSR after that module was partially reconfigured.
- For UltraScale™ and UltraScale+ devices: because of the improved GSR
controls, both Pblocks automatically use
automatically creates legal, reconfigurable Pblocks. See Automatic Adjustments for Reconfigurable Partition Pblocks (for 7 series devices) or Automatic Adjustments for PU on Pblocks (for UltraScale™ and UltraScale+
devices) for more information.
The GSR capabilities are embedded within the partial bitstreams, so
nothing extra must be done to include this feature during reconfiguration. However,
because this process uses the
SHUTDOWN sequence (masked
to the reconfiguring region only), the external
pin are pulled
LOW when reconfiguration starts, then
HIGH when it successfully completes. This behavior
must be considered when setting up the board. Using the
DONEO is not an option to
DONE pin from changing state, because this
block is disabled during shutdown. Nor can
used for other purposes, such as generating a configuration clock for partial
RESET_AFTER_RECONFIG is used.
To open the GSR mask for only the dynamic region when reconfiguration occurs, the mask for the entire design begins as closed after the initial configuration. Each partial bitstream opens the mask for the target region, loads new configuration data, issues a GSR event for this region, then closes the mask. For UltraScale devices only, this process is split between two bitstreams -- see Clearing Bitstreams for more information. Because the mask is closed when reconfiguration is not occurring, full-device access to GSR is not permitted.
For 7 series devices only, an alternative approach would be to forgo this property and apply a local reset to any reconfigured logic that requires initialization to function properly. This approach does not require vertical alignment to clock region boundaries. Without GSR or a local reset, the initial starting value of a synchronous element within a reconfigured module cannot be guaranteed.