AMD recommends avoiding direct timing paths between multiple reconfigurable partitions (RPs) for the following reasons:
- If the boundary signal between the RPs does not have a static boundary leaf cell, the DFX flow must deposit a PPLOC on both RPs. As a result, tool capabilities like expanded routing with PPLOC reduction cannot be used. The presence of PPLOCs also causes routability challenges in subsequent reconfigurable module (RM) implementations, also known as child implementations in Vivado Project Mode.
- If the timing paths across an RP do not have a static boundary leaf cell, there might be a combination of RMs in two RPs that do not meet timing. The omission of a synchronous timing point in the static portion of the design can also lead to timing and hardware failures depending on the RMs that are currently loaded. The HDPR-34 and HDPR-35 DRCs flag this issue.