Clock Region Sharing Between Multiple Reconfigurable Pblocks - 2023.2 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
UG909
Release Date
2023-11-15
Version
2023.2 English

Clocking resources in an RCLK row can be shared by two reconfigurable partitions. Hence, it is possible to share a clock region between two reconfigurable partitions (one RP above the RCLK row and one RP below the RCLK row). You can share more than two reconfigurable partitions in a clock region if only at most two of them have internal clocking resources. Sharing a clock region between more than two reconfigurable partitions, where all of them have clocking resources results in a DRC error. The error happens because clock routing expansion of all RPs tries to pull in clocking resources from the same RCLK row of that clock region which is not supported. RCLK row clock tracks sharing is allowed only with two RPs and anything more than that will result in DRC error.

In the following figure, two reconfigurable partitions rp1 and rp2 share the same clock region X3Y2. Both RPs have internal clock net (yellow and magenta color highlighted). Both the clocks share the same RCLK row.
Figure 1. Sharing Clock Region between Multiple Reconfigurable Pblocks
Figure 2. Schematic View of Two Reconfigurable Modules With An Internal Clock
Figure 3. Magnified View of Device. Top Half of RCLK is Used by One Partition’s Clock Net And Bottom Half is Used By Other Partition’s Clock Net