In a disjoint Pblock, the part of the reconfigurable Pblock in the fabric region that is away from the clocking resources at the bottom of the device is referred to as the primary region. The part of the reconfigurable Pblock in the fabric region that is adjacent to the clock sources, which includes the sites of the clock sources, is referred to as the secondary region. The following figure shows an example.
To create the disjoint Pblock, use the following steps:
- Create the top Pblock that defines the reconfigurable partition. Add the
EXCLUDE_PLACEMENT and CONTAIN_ROUTING properties.
The following figure shows the statistics for the top disjoint pblock_bramctrl_rm in the Device view with the Pblock highlighted in orange. The primary region of the Pblock is in SLR1. The secondary region of the Pblock is in the horizontal super row (HSR).Figure 2. Disjoint Pblock Example
- Create a child Pblock that defines the primary region. The child
Pblock must match the ranges of the main contiguous reconfigurable Pblock. Omit the
ranges for the clocking resources. The clocking resources must be part of the
secondary region. You can use the
get_dfx_footprintcommand to get the child Pblock site range. For example:
get_dfx_footprint -site_type fsr -of_objects [get_cells design_0_i/bramctrl_rm]
Follow these guidelines when creating the child Pblock:
Note: The Vivado tools automatically apply SNAPPING_MODE = NESTED to the child Pblock if the parent Pblock has SNAPPING_MODE = ON.
- Use the PARENT property to define the relationship between
this new child Pblock and the top RP Pblock. For
set_property PARENT <parent_Pblock> [get_Pblocks <child_Pblock>]
- Do not use the EXCLUDE_PLACEMENT and CONTAIN_ROUTING properties for the child Pblock.
- Only one child Pblock is supported.
- Use the PARENT property to define the relationship between this new child Pblock and the top RP Pblock. For example:
- Optionally, add multiple parallel or nested Pblocks under the child Pblock to do more detailed floorplanning.
You must make specific cell assignments in the primary and secondary regions. This ensures that the Vivado placer does not place non-clock logic in the secondary region of a disjoint Pblock. If this non-clock logic connects to logic in the primary region of the disjoint Pblock, unroutes might occur because there are no standard, non-clock routing resources to bridge the gaps between the sections. Follow these guidelines when making cell assignments:
- Assign all the non-clock cells to the child Pblock or the primary region. Exclude assignment of the clock control logic from the child Pblock.
- Extend the secondary region into the fabric region to place the clock control logic (for example, Safe Clock StartUp) near the clock sources placed in the HSR.
- Use the
get_dfx_footprintcommand to get the non-clock cells that need to be assigned to the child Pblock. For example:
get_dfx_footprint -cell_type non_clock -of_objects [get_cells design_0_i/bramctrl_rm]
The following figure shows the Pblock statistics for the pblock_bramctrl_rm after creating the pblock_bramctrl_rm_guided_floorplan_child Pblock. All the resources are now assigned to the child Pblock except the clock resources like GLOBAL CLOCK BUFFERS, MMCM, and the 16 registers of the Safe Clock StartUp logic, which remain assigned to the parent Pblock.
In some cases, a non-clock boundary net must drive logic in both the primary region and secondary region. When this occurs, the Vivado tools need two separate PPLOCs for proper routing of the boundary net to each region. If the design has a single boundary pin for this boundary net, you must split the boundary pin into two. One pin must be used by the boundary net to drive the loads of the logic that is assigned to the primary region, and the other pin must be used to drive the loads in the secondary region. AMD recommends planning the hierarchy of the reconfigurable module so that the clock and clock control logic are in one module, which makes splitting this boundary pin straightforward. For example designs that show disjoint Pblock creation methodologies, see the Versal Device DFX Debug Tutorials available from the GitHub repository.
The following figure shows an example of the ext_reset_in_1 boundary net, which needs to drive the logic in the primary region and secondary region. The ext_reset_in_1 boundary pin of the RM bramctrl_rm is split into ext_reset_in_1_1 and ext_reset_in_1 so that two PPLOCs are created, one for each disjoint Pblock region.
If you do not follow the preceding recommended methodologies, the violations are reported by the following disjoint Pblock DRCs.
The disjoint Pblock '%ELG'
for Reconfigurable Module '%ELG' has more than one %STR logic
regions which have no overlapping routing footprints. A disjoint
Pblock can have only one HSR and one fabric logic region. Use
get_dfx_footprint command to debug further and modify the
|The disjoint Pblock has more than one primary or secondary region that are disjoint.
The net '%ELG' is connected
to both HSR and fabric regions through one interface pin '%ELG' of
Recongigurable Module '%ELG' of disjoint Pblock '%ELG'. This is an
unrouteable situation. Please edit the design to have separate
interface pins for HSR and fabric region of the disjoint
|The boundary pin of a boundary net that drives both regions of a disjoint Pblock is not split.
The connection of interface
pin '%ELG' of the reconfigurable module '%ELG' has changed from %STR
region of the disjoint Pblock '%ELG' in parent implementation to
%STR region. This is an unrouteable situation. Please change the
connectivity of interface pin and ensure that all interface pins are
connected to the same disjoint region as in the parent
|There is a change in pin connections between the primary and secondary region in the child implementation when compared with parent implementation.
HDPR - 135
Pblock %ELG has has a child Pblock %STR with EXCLUDE_PLACEMENT set
to 1. When disjoint Pblocks are used for DFX, only a single child
Pblock is permitted, to define the primary region without
EXCLUDE_PLACEMENT. Please reset the the property using :
'set_property EXCLUDE_PLACEMENT false [get_Pblocks
|The child Pblock includes the EXCLUDE_PLACEMENT property.
Placement of logic within
Reconfigurable Partition Pblock %ELG will require non-clock route
connections between disjoint regions. This is an unroutable
situation. Please adjust Pblock construction or location constraints
to ensure all non-clock routing for the logic in this Reconfigurable
Partition can be contained within the contiguous child Pblock %ELG
in this disjoint Pblock case %STR
|A non-clock connection exists between the primary region and secondary region.
Logical elements that must
be contained in Reconfigurable Partition Pblock %ELG are not
included in child Pblock %ELG. When disjoint Pblocks are used for
DFX, the only elements permitted outside the child Pblocks are
clocking resources and elements that have explicit LOC constraints.
Please move these elements to child Pblock %ELG or provide explicit
|Some non-clock elements are not assigned to the child Pblock.
HDPR - 134
Pblock %ELG has no child Pblock. When disjoint Pblocks are used for
DFX, a single child Pblock is required, to define the primary
region. Please add a single child Pblock under %ELG to define the
|The child Pblock is missing.
Child Pblock %ELG of
Reconfigurable Partition Pblock %ELG occupies a non-contiguous area.
When disjoint Pblocks are used for DFX, the child Pblock must occupy
a contiguous area. It is strongly recommended that this area aligns
with the primary area of the parent Pblock.
|The child Pblock is disjoint.
HDPR - 127
Pblock %ELG has multiple child Pblocks %STR. When disjoint Pblocks
are used for DFX, only a single child Pblock is permitted, to define
the primary region. Please remove all but one of these child Pblocks
under %ELG to define the contiguous area.
|There is more than one child Pblock with the same top reconfigurable partition Pblock as the parent Pblock.