Creating Pblocks for UltraScale and UltraScale+ Devices - 2023.2 English

In the UltraScale architecture, the smallest unit that can be reconfigured is smaller than in previous architectures. The minimum required resources for reconfiguration varies based on the resource type and are referred to as a programmable unit (PU). Because adjacent sites share a routing resource (or interconnect tile) in UltraScale devices, a PU is defined in terms of pairs.

Following are examples of some of the minimum PU that can be reconfigured based on the site types:

CLB PU

2 adjacent CLBs and the shared interconnect

Block RAM PU

1 RAMBFIFO36 and 2 BRAM18, 5 adjacent CLBs, and the shared interconnect

URAM PU

1 URAM, 30 adjacent CLBs (15 on each side), and the shared interconnect

DSP PU

1 DSP, the 5 adjacent CLBs, and the shared interconnect

IOB PU

The I/O of the full height of the clock_region includes BITSLICE_CONTROL, BITSLICE_RX_TX, BITSLICE_TX, BUFGCE, BUFGCE_DIV, BUFGCTRL, IOB, MMCME3_ADV, PLLE3_ADV, PLL_SELECT_SITE, RIU_OR, HBM_REFCLK etc., the adjacent 60 CLBs and the shared interconnect

GTY PU

A full GT quad (4 GT_CHANNEL and 1 GT_COMMON), the adjacent 60 CLBs, 24 BUFG_GTs, 15 BUFG_GT_SYNCs, and the shared interconnect

GTM_DUAL PU

GTM_DUAL, GTM_REFCLK, 24 BUFG_GTs, 15 BUFG_GT_SYNCs, 60 CLB tiles and shared interconnect

PCIe® PU

1 PCIE40E4 or PCIE4CE4, 120 adjacent CLBs (60 on each side) and the shared interconnect

CMAC PU

1 CMACE4, 120 adjacent CLBs (60 on each side) and the shared interconnect

Interlaken PU

1 ILKNE4, 120 adjacent CLBs (60 on each side) and the shared interconnect

CONFIG PU

1 CONFIG_SITE, 120 adjacent CLBs (60 on each side) and the shared interconnect

Note: The CONFIG_SITE contains many single site resources including ICAP, STARTUP, BSCAN, FRAME_ECC, DNA_PORT, EFUSE_USR and MASTER_JTAG, and cannot be broken up further.

HBM BLI PU

1 BLI_HBM, 15 adjacent CLBs and the shared interconnect.