During Abstract shell Creation, AMD Vivado™ can infer false path constraints on some of the static logic paths which are already placed and routed in the platform compile. There are situations where a specific static logic topology is retained in the abstract shell, however does not require to be timed again because these are not in the input/output cone of the RM compile. These false path constraints are expected to be created only on static logic which are outside the input/output cone of the reconfigurable module thereby users should not see any impact of these false paths during RM compile using abstract shell.
The initial bitstream used for downloading static region logic in hardware is created from the platform compile where the static region was implemented with user constraints. Hence these tool created false path constraints in the static region is never seen in the hardware. During RM compile, these false paths enables the RM compile to focus only on the RM logic along with its input and output cones.