Most of the clocking guidelines of UltraScale+ stay the same for Versal devices. However, the Versal device clocking structure provides more clocking primitives and guidelines to better manage skew and meet timing closure more easily. For more information on the clocking structure in Versal devices, see this link in the Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387).
|Clocks with driver and loads inside the reconfigurable partition
|Clocks with nets crossing the reconfigurable
module cell boundary
Following is the DFX behavior for different categories of clock nets:
Internal RM Clock Net
- Clock root is placed at the center of loads inside RP Pblock.
- More flexibility for placement and routability of the internal clock of RM in subsequent implementation.
- Global clock partitioning is only required to allocate enough clock regions for a given net to drive RM loads. This can reduce the chance of clock partitioning errors.
- This is recommended whenever possible to achieve better skew and optimal clock root placement.
Boundary Clock Net
- Boundary clock net track gets locked down after first implementation.
- The PPLOCs of the boundary clock nets are distributed to all clock regions covered by the RP Pblock.
- Global clock partitioning requires prerouting boundary clocks to every clock region within the RP even if the loads can fit into a single clock region.
- The clock root of the boundary clock net can be placed anywhere in the device, because it can drive both static and RP loads. If the loads of boundary clock are located more in static region, it is possible that the clock root is placed in static region.
- If the first implementation is done using training logic in
the RP Pblock, it is possible that boundary clock nets are locked down after
first implementation with sub-optimal clock root location. AMD recommends using the
USER_CLOCK_ROOTconstraint on the boundary clock net to manually constrain the