This section covers notable changes in Versal clocking. Versal allows clock tile splitting among multiple RPs. However, this is taken care by the tool. You only need to range the clock sources like MMCM and BUFGs to the Pblock, and DFX flow automatically pulls in the required clocking tiles for routing.
The following figure Clock Tile Partition
RCLK row and
column sharing among multiple reconfigurable partitions. The
RCLK row sharing among two reconfigurable partitions allows sharing the
clock region between two RPs (one above the
RCLK and one
VNOC tiles are also shared between multiple reconfigurable partitions.
However, if more than two RPs compete to find clock routing solution in a single VNOC
column, it might cause unroutable situation. If there are more than two RPs, try to keep
a clock region gap between them so that internal clocks of all the RPs do not compete
for solution in same