In a DFX design, the network on chip (NoC) networks can be distributed across both static and dynamic regions of the design, or they can be contained within a single region. The following figure shows four simplified NoC networks to illustrate this concept.
- This NoC topology includes both the source (NMU) and target (NSU) components located within the static region. During the parent implementation phase of the DFX flow, the Quality of Service (QoS) parameters for this network are established. The NoC compiler solution to meet the QoS requirements includes factors like read bandwidth, write bandwidth, latency, and location, and this solution is locked down within the static region. This ensures that subsequent child RM implementations adhere to these established QoS parameters.
- In this NoC topology, the source component (NMU) is located in the static region, and the target component (NSU) is in the dynamic region. To facilitate communication across the DFX partition, peripherals within the static region can access the NoC network through the ingress Endpoint NMU and exit through the egress Endpoint NSU to communicate with peripherals in the dynamic region.
- This NoC topology is similar to the Network-1 topology except that the source component (NMU) is located in the dynamic region, and the target component (NSU) is located in the static region. One common use case for this topology is the programmable logic (PL) peripherals in the dynamic region accessing the DDR memory resources located in the static region. In Versal devices, DDR memory controllers are NoC target Endpoints (NSUs).
- With regard to DFX design flexibility, this NoC topology is the most versatile. Both Endpoints of the network, the source component (NMU) and the target component (NSU), are positioned within the dynamic region. As a result, this topology can undergo a complete reconfiguration to align with the specific requirements of each reconfigurable module.