Timing constraints for a partially reconfigurable design are similar to timing constraints for a traditional flat design. The primary clocks and I/Os must be constrained with the corresponding constraints. For more information on these constraints, see this link (for defining clocks) and this link (for constraining I/O delays) in the Vivado Design Suite User Guide: Using Constraints (UG903).
After the correct constraints are applied to the design, run static timing analysis to verify the performance of the design. This verification must be run for each RM in the overall static design. For more information on how to analyze the design, see the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).
The Vivado Design Suite includes the capability
to run cell level timing reports. Use the
report_timing_summary to focus timing analysis on a specific RM. This is
especially useful on configurations where the static design has been imported and locked
from a prior configuration.
There is a Partition column added to the timing reports generated by
report_timing_summary. It helps identify if failing paths are within static, an RM, or crosses an RP boundary. Both of these commands have a new
-no_pr_attribute switch to turn this new functionality off. This can be useful if, for example, scripts are being used to parse the timing reports and are negatively affected by this new column.