The AMD Vivado™ Dynamic Function eXchange (DFX) design flow is similar to a standard design flow, with some notable differences. The implementation software automatically manages the low-level details to meet silicon requirements. You must provide guidance to define the design structure and floorplan. The following steps summarize processing a DFX design:
- Synthesize the static and reconfigurable modules (RM) separately. See Synthesis for more information.
- Create physical constraints (Pblocks) to define the reconfigurable regions. See Create a Floorplan for the Reconfigurable Region for more information.
- Set the
HD.RECONFIGURABLEproperty on each reconfigurable partition (RP). See Define a Module as Reconfigurable for more information.
- Implement a complete design (static and one RM per RP) in context. See Implementation for more information.
- Save a design checkpoint for the full routed design. See Implementation for more information.
- Remove RMs from this design and save a static-only design checkpoint. See Implementation for more information.
- Lock the static placement and routing. See Preserving Implementation Data for more information.
- Add new RMs to the static only design and implement this new configuration, saving a checkpoint for the full routed design.
- Repeat Step 8 until all RMs are implemented.
- Run a verification utility (
pr_verify) on all configurations. See Verifying Configurations for more information.
- Create bitstreams for each configuration. See Bitstream Generation for more information.