Configuring AXI MIG - 2023.2 English

ISE to Vivado Design Suite Migration Guide (UG911)
Document ID
UG911
Release Date
2023-11-01
Version
2023.2 English
  1. In the Block Properties, click the Properties tab, expand CONFIG, and scroll down to XML_INPUT_FILE.
  2. Provide the absolute path of the modified mig.prj file and press Enter.

    The tool loads the XML and provides error messages if the PRJ file is incorrect.

    Tip: It might take a 30 seconds or so for this operation to complete.
  3. Double-click the mig_7series_0 instance in the block diagram to verify the MIG settings.

    Because the clocking/reset for the memory controller is handled in the IP, MIG must configure the input and output clocks and reset for the design.

  4. Verify that the Options for Controller 0 are correct (such as memory speed and memory selection). If the settings do not look correct for the board memory, change them.
  5. Verify the AXI Parameter Options, C0, are correct. Ensure that Narrow Burst Support is set correctly, based on the XPS design. If you are unsure, set this parameter to 1.
  6. In the Memory Options for Controller 0, configure the input clocking/reset.
    1. For the Input Clock Period, select the differential or single-ended clock input frequency, based upon the board type. On the KC705 board, the correct setting is 5000 ps (200 MHz).
    2. If the existing XPS design contained MicroBlaze or other IP, additional fabric clocks are needed. Click the Select Additional Clocks check box.
      Tip: Typically, additional clocks are not needed if the original XPS design was created using BSB.
    3. Typically, a MicroBlaze device design has 100 MHz clocks. For Clock 0, select 10000 ps (100.00000 MHz). This is used for the MicroBlaze portion of the design.
    4. Verify the other options for the memory controller.
    5. Click Next.

      The system clock selects the method used to deliver the input clock to the memory controller. The KC705 board uses a Differential clock input.

  7. Select Differential for the System Clock.

    You can generate the reference clock from the internal MMCM if it can generate a 200 MHz clock.

  8. Select Use System Clock for the Reference Clock.
  9. Set the System Reset Polarity based upon the board type (active-Low or active-High).
    1. Select the appropriate setting for the board in use. Active-High is correct for the KC705 board.
    2. Verify the other options for the memory controller.
    3. Click Next.
  10. Keep validating settings and clicking Next until the Pin/Bank Selection Mode dialog box opens.
    1. In the Pin/Bank Selection Mode dialog box, select Fixed Pin Out and click Next.

      The pinout is already defined if the MIG settings are correct for the memory, and the project file was modified correctly.

    2. Select Validate.
    3. After the pinout is validated correctly, click OK, even if INFO messages exist.
    4. Click Next.
  11. In the System Signals Selection
    1. Select the sys_clk_p/n pins that are used on the board. (The KC705 uses Bank Number 33 Pin AD12/AD11.) The clk_ref is already connected to an internal signal.
    2. Connect the Status Signals as needed, based on the design.
  12. Click Next until you reach the Memory Model License agreement.
    1. Accept the Memory Model License agreement.
    2. Click Generate.