Designing with a platform board selected as the part: - 2023.2 English

1. From the Board tab drag and drop the desired clock, such as the System differential clock, for the KC705 board on the block design canvas.
   
   

   

   
   
2. Likewise drag and drop the FPGA Reset from the Board tab to the block design canvas.

For more information on the platform board flow, refer to the section Using the Board Flow in IP integrator in Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994).