You can mark a signal for debug by selecting a net in the block design, right-clicking, and selecting Mark Debug in the IP integrator. This preserves the nets marked for debug by putting the appropriate net-preserving attributes in the generated HDL code. Then the design can be synthesized, and debug core(s) can be inserted in the synthesized netlist. An ILA can also be instantiated in the Block Design and AXI interfaces or individual I/O ports can be hooked up to the ILA for monitoring later.
Zynq 7000 platform processor-based and MicroBlaze processor-based designs also support cross-trigger functionality. This essentially means that the processors have the ability to trigger and be triggered by the Vivado Integrated Logic Analyzer.
Refer to the following documents for more information: