set design_name design_top
#read inputs
read_verilog { $design_name.v source2.v source3.v }
read_vhdl -lib mylib { libsource1.vhdl libsource2.vhdl }
read_xdc $design_name.xdc
#run flow and save the database
synth_design -top $design_name -part xc7v585tffg1157-21
write_checkpoint -force ${design_name}_post_synth.dcp
opt_design
place_design
write_checkpoint -force ${design_name}_post_place.dcp
report_utilization -file post_place_util.txt
route_design
#Reports are not generated by default
report_timing_summary -file post_route_timing.txt
#Save the database after post route
write_checkpoint -force ${design_name}_post_route.dcp
#Check for DRC
report_drc -file post_route_drc.txt
# Write Bitstream
write_bitstream -force ${design_name}.bit