The AUTOPIPELINE_INCLUDE property specifies the name of another AUTOPIPELINE_GROUP to include when applying the AUTOPIPELINE_LIMIT. The normal usage scenario is in the forward and response shakehands protocal paths, one direction is defined as a “forward” group using AUTOPIPELINE_GROUP, and the other direction is defined as a primary “response” group using AUTOPIPELINE_GROUP, while adding reference to the forward group, so the round-trip path would share the maximum limit as defined.
UltraScale, UltraScale+, Versal Adaptive SoCs.
- Nets (get_nets)
- Cells (get_cells)
Each single net should be directly driven by a flip-flop, and the fanout load can only be 1.
<group_name>: This is a unique string value that can be assigned to one or more nets. The signals with a same auto-pipeline include group name must receive an equal number of auto-inserted pipeline flip-flops.
- VHDL Example Syntax
attribute autopipeline_include : string; attribute autopipeline_group : string; attribute autopipeline_limit : integer; signal mywire: std_logic_vector(2 downto 1); signal mybus: std_logic_vector(2 downto 1); attribute autopipeline_group of mywire: signal is "sub_group"; attribute autopipeline_group of mybus: signal is "primary_group"; attribute autopipeline_include of mybus: signal is "sub_group"; attribute autopipeline_limit of mybus: signal is "12”;
- Verilog Example Syntax
(* autopipeline_group="sub_group”*) wire mywire; (* autopipeline_group="primary_group", autopipeline_limite= 12, autopipeline_include="sub_group"*) wire mybus;
- XDC Example Syntax
set_property AUTOPIPELINE_GROUP primary_group [get_nets mywire] set_property AUTOPIPELINE_INCLUDE sub_group [get_nets mywire]
The sub_group is included in the primary_group, and shares the maximum limit of 12 stages.
- Place Design
- Phys Opt Design