The Boundary Logic Interface (BLI) constraint instructs the Vivado placer to place a flip flop cell into the BLI resources that exist at the interface between Programmable Logic and XPIO/AI Engine resources. BLI resources can help optimize the timing of the interface. The Vivado placer will only place the flip-flop cell into the BLI resource if connectivity, control set, and initial value criteria are met.
Versal Adaptive SoCs
Flip-flop cells (
get_cells) connected to applicable XPIO or AI Engine primitives.
- The flip-flop cell will be placed into the BLI resource if connectivity, control set, and initial value criteria are met.
- The flip-flop cell will not be placed into the BLI resource (default).
- Currently unsupported.
- VHDL Syntax
- Verilog Syntax
- XDC Syntax
set_property BLI <TRUE | FALSE> [get_cells <ff_cells>]
XDC Syntax Examples:
# Use BLI Flip flop set_property BLI TRUE [get_cells myHier/myBliFlop]