The BLOCK_SYNTH property lets you assign synthesis properties to an instance of a hierarchical module in the design, to provide a greater degree of control over global synthesis. With BLOCK_SYNTH you can specify different optimizations for two different instances of the same module, and process them during global synthesis.
By setting a BLOCK_SYNTH on an instance, you will be affecting that instance and everything below it. For example, if a hierarchical module has other modules nested within it, those modules are also affected by the BLOCK_SYNTH property. However, you can also assign another BLOCK_SYNTH property to the nested module to change its settings, or restore it to the default value.
When working with IP, you can use the BLOCK_SYNTH property when the IP is specified for global synthesis.
You can use the block-level synthesis strategy to synthesize different levels of hierarchy with different synthesis options in a top-down flow. You can specify constraints for the full design, and also specify unique constraints for specific instances of hierarchical modules. For more information on block-level synthesis, refer to Vivado Design Suite User Guide: Synthesis (UG901).
Architecture Support
All architectures.
Applicable Objects
Hierarchical modules (get_cells)
Value
BLOCK_SYNTH.<option_name>: Indicates that the module instance
should be synthesized with the specified parameters or options. The list of options
that can be specified can be found in the
Vivado
Design Suite User Guide: Synthesis (UG901).
Syntax
- VHDL Syntax
-
Not applicable
- Verilog Syntax
-
Not applicable
- XDC Syntax
-
Set the BLOCK_SYNTH property in the XDC file using the following syntax:
set_property BLOCK_SYNTH.<option_name> <value> [get_cells <instance_name>]Where:
-
<option_name>specifies the option to be defined. -
<value>specifies the value of the option. -
<instance_name>specifies the instance name of an hierarchical cell, block, or IP, to apply the property to.
For example, you can define the following in an XDC file:
set_property BLOCK_SYNTH.RETIMING 1 [get_cells U1] set_property BLOCK_SYNTH.STRATEGY {AREA_OPTIMIZED} [get_cells U2] set_property BLOCK_SYNTH.STRATEGY {AREA_OPTIMIZED} [get_cells U3] set_property BLOCK_SYNTH.STRATEGY {DEFAULT} [get_cells U3/inst1] -
Affected Steps
- Synthesis