CELL - 2023.2 English

Description

A cell is an instance of a netlist logic object, which can either be a leaf-cell or a hierarchical cell. A leaf-cell is a primitive, or a primitive macro, with no further logic detail in the netlist. A hierarchical cell is a module or block that contains one or more additional levels of logic, and eventually concludes at leaf-cells.

Related Objects

As seen in the figure above, cells have PINs which are connected to NETs to define the external netlist. Hierarchical cells also contain PORTs that are associated with PINs, and which connect internally to NETs to define the internal netlist of the hierarchy.

Leaf CELLs are placed, or mapped, onto device resources on the target AMD FPGA. The CELL can be placed onto a BEL object in the case of basic logic such as flops, LUTs, and MUXes; or can be placed onto a SITE object in the case of larger logic cells such as BRAMs and DSPs. BELs are also collected into larger SITEs, called SLICEs, so a cell can be associated with a BEL and a SITE object. SITEs are grouped into CLOCK_REGIONs and TILEs.

CELLs are also associated with TIMING_PATHs in the design, and can be associated with DRC_VIOLATIONs to help you quickly locate and resolve design issues.

You can query the CELLs associated with pins, timing paths, nets, bels, clock regions, sites, or DRC violations:

get_cells -of [get_nets clk]

Properties

There are different types of leaf-cell objects, defined by the PRIMITIVE_GROUP, PRIMITIVE_SUBGROUP, and PRIMITIVE_TYPE properties as enumerated below.

All cells have a common set of properties; but each cell GROUP, SUBGROUP, and TYPE can also have unique properties. You can report the properties for specific types of CELL objects by filtering on the PRIMITIVE_GROUP, PRIMITIVE_SUBGROUP or PRIMITIVE_TYPE property value.

PRIMITIVE_TYPE is an enumerated property, the defined values of which can be returned with the list_property_value command:

list_property_value -class cell PRIMITIVE_TYPE

However, a design will probably not contain cells for each defined PRIMITIVE_TYPE. The following Tcl code searches hierarchically through a design and returns unique occurrences of the PRIMITIVE_TYPE property for all the cells in the design.

foreach x [get_cells -hierarchical *] {
lappend primTypes [get_property PRIMITIVE_TYPE $x] } join [lsort -unique $primTypes] \n

From the returned list, $primTypes, you can report the properties for a specific PRIMITIVE_TYPE using the following command:

report_property -all [lindex [get_cells -hier -filter {PRIMITIVE_TYPE == <val>}] 0]

Where <val> represents the PRIMITIVE_TYPE of interest. For example, to return the properties of the BLOCKRAM.BRAM.RAM18E2 type cell:

report_property -all [lindex [get_cells -hier -filter {PRIMITIVE_TYPE == "BLOCKRAM.BRAM.RAMB18E2"}] 0]

You can also return the properties from a hierarchical cell using the following Tcl command:

report_property -all [lindex [get_cells -hier -filter {!IS_PRIMITIVE}] 0]

Of course, you can also simply return the properties for the specific cell of interest:

report_property -all [get_cells <cell_name>]