By default, Vivado synthesis infers an input buffer and global clock buffer (IBUF/BUFG) combination for clocks ports. However, you can use the IO_BUFFER_TYPE and the CLOCK_BUFFER_TYPE properties together to direct the Vivado synthesis tool to change the default buffer types, to an IBUF/BUFR pair, no input buffer with a BUFIO clock buffer, or to eliminate the buffers Zynq UltraScale+ MPSoCaltogether.
Mandatory logic optimization (MLO), which occurs at the beginning of
opt_design supports the use of the CLOCK_BUFFER_TYPE property to
insert global clock buffers. Commonly used values include BUFG for 7 series, and BUFG and
BUFGCE for UltraScale, UltraScale+, and Versal devices. The value NONE can be used for all
architectures to suppress global clock buffer insertion through MLO and
opt_design. For the values BUFG and BUFGCE,
opt_design and MLO inserts the corresponding buffer
type to drive the specified net.
The CLOCK_BUFFER_TYPE property indicates what type of clock buffer to infer for the specified net or port objects. The IO_BUFFER_TYPE property indicates whether to infer an input or output buffer for the port.
CLOCK_BUFFER_TYPE can be defined in the RTL or in the XDC. When specified in the RTL, the property can be attached to a port. After synthesis, the property CLOCK_BUFFER_TYPE should be attached to the net driven by the input buffer.
- Ports (
- Apply CLOCK_BUFFER_TYPE to any top-level clock port to describe what type
of clock buffer to use, or to use no clock buffer. For 7 series, UltraScale and Ultra Scale Plus, the property
can only be set on ports inside RTL and will not be used by
opt_designwhen set on ports through XDC. For Versal Adaptive SoCs,
opt_designonly supports CLOCK_BUFFER_TYPE on ports through XDC for OOC implementation. For any other flow, the property should be set on the net driven by the top-level port.
- Nets (
- Apply CLOCK_BUFFER_TYPE to any signal connected to a top-level clock port (synthesis) or any net (logic optimization) to describe what type of clock buffer to use, or to use no clock buffer.
BUFR: Directs the tool to infer the specified clock buffer for clock ports or nets.Note: For Versal architecture, when the net only drives non-clock pins, the property value
BUFGCEresults in a BUFG_FABRIC being inferred. If the net drives one or more clock pins, then a BUFGCE is inferred.
BUFG_FABRIC(Versal Only): Directs the tool to infer a BUFG_FABRIC for the nets. This property value preferably be set for nets driving non-clock pins. When the value
BUFG_FABRICis used on non-Versal architectures, no buffer is inserted and the placer fails with the Vivado error
NONE: Directs the tool to not infer any clock buffers for the clocks.Note: Use with IO_BUFFER_TYPE “NONE” to prevent Vivado synthesis from inferring any buffers.
- Verilog Syntax
(* clock_buffer_type = "none" *) input clk1;
- VHDL Syntax
entity test is port( in1 : std_logic_vector (8 downto 0); clk : std_logic; out1 : std_logic_vector(8 downto 0)); attribute clock_buffer_type : string; attribute clock_buffer_type of clk: signal is "BUFR"; end test;
- XDC Syntax
set_property CLOCK_BUFFER_TYPE BUFMR [get_nets <net_name>]
- Opt Design