While all registers support resets and clock enables, their use can significantly
affect the end implementation in terms of performance, utilization, and power.
Designs with a large number of unique control sets can have fewer options for
placement, resulting in higher power and lower performance. The CONTROL_SET_REMAP
property is placed on register primitives to trigger a control set reduction on a
specific register during logical optimization (
When a logic path ends at a fabric register (FD) clock enable, or synchronous set/reset, the property on the register instructs Vivado logic optimization to map the enable or reset signal to the data pin (D), which has a dedicated LUT connection and can be faster. If possible, the logic is combined with an existing LUT driving the D-input to prevent the insertion of extra levels of logic.
- Architecture Support
- All architectures.
- Applicable Objects
- Cells (
- Remaps the EN input to the D-input.
- Remaps the synchronous S or R input to the D-input.
- Same as ENABLE and RESET combined.
- Do nothing. This is the default, and is the same as if the property were not set on the cell.
- Verilog Syntax
- VHDL Syntax
- XDC Syntax
set_property CONTROL_SET_REMAP <value> [get_cells <cell_pattern>]
XDC Syntax Example
# Specifies control set reduction based on Enable signals set_property CONTROL_SET_REMAP ENABLE [get_cells ff*]
- Opt Design