DIRECT_ENABLE - 2023.2 English

Apply DIRECT_ENABLE on an input port or other signal to have it go directly to the enable line of a flop when there is more than one possible enable or when you want to force the synthesis tool to use the enable lines of the flop.

Architecture Support

All architectures.

Applicable Objects

The DIRECT_ENABLE attribute can be placed on any port or signal.

Values

TRUE (or YES)

Use the enable lines of the flop.

FALSE (or NO)

Do not direct synthesis to use the enable line of a flop. This is the default.

Syntax

Verilog Syntax

(* direct_enable = “yes” *) input ena3;

VHDL Syntax

entity test is port(
in1 : std_logic_vector (8 downto 0); 
clk : std_logic;
ena1, ena2, ena3 : in std_logic
out1 : std_logic_vector(8 downto 0)); 
attribute direct_enable : string;
attribute direct_enable of ena3: signal is "yes"; end test;

XDC Syntax

set_property direct_enable yes [get_nets –of [get_ports ena3]]

Affected Steps

• Synthesis