DIRECT_RESET - 2023.2 English

Apply DIRECT_RESET on an input port or other signal to have it go directly to the RESET line of a flop when there is more than one possible reset or when you want to force the synthesis tool to use the reset lines of the flop.

Architecture Support

Architecture Support

Applicable Objects

The DIRECT_RESET attribute can be placed on any port or signal.

Values

TRUE (or YES)

Direct synthesis to use the RESET line of a flop.

FALSE (or NO)

Do not direct synthesis to use the RESET line. This is the default.

Syntax

Verilog Syntax

(* direct_reset = "yes" *) input rst3;

VHDL Syntax

entity test is port(
in1 : std_logic_vector (8 downto 0); 
clk : std_logic;
rst1, rst2, rst3 : in std_logic
out1 : std_logic_vector(8 downto 0)); 
attribute direct_reset : string;
attribute direct_reset of rst3: signal is “yes”; end test;

XDC Syntax

set_property direct_reset yes [get_nets –of [get_ports rst3]]

Affected Steps

• Synthesis