DQS_BIAS - 2023.2 English

DQS_BIAS is a property of the top-level port driving a differential input buffer or bidirectional buffer primitive (IBUFDS, IOBUFDS). The DQS_BIAS attribute provides an optional DC bias at the inputs of certain pseudo-differential I/O standards (DIFF_SSTL) and true differential I/O standards (LVDS). If nothing is driving the buffer, DQS_BIAS provides a weak bias so that the logic state is not unknown in pseudo-differential I/O standards. DQS_BIAS provides a pull-up/pull-down feature required for some DQS memory interface pins.

Recommended: Because DQS_BIAS affects the logic function of the design, it should be defined via a Verilog parameter statement, or VHDL generic_map, to correctly support simulation. However, it is also supported as an XDC property.

In high-performance (HP) I/O banks, DQS_BIAS can be used to support differential inputs, such as LVDS. The use of DQS_BIAS can provide the DC-bias in AC-coupled LVDS applications. See the 7 Series FPGAs SelectIO Resources User Guide (UG471), or the UltraScale Architecture SelectIO Resources User Guide (UG571) for more information.

Note: DQS_BIAS is not available in high-range (HR) I/O banks for true differential I/O standards.

Architecture Support

All architectures.

Applicable Objects

Ports (get_ports)
- Ports driving differential Input buffers: IBUFDS, IBUFDS_IBUFDISABLE, IBUFDS_INTERMDISABLE, IBUFDSE3
- Ports driving differential IO buffers: IOBUFDS, IOBUFDS_DCIEN, IOBUFDS_INTERMDISABLE, IOBUFDSE3, IBUFGDS

Values

TRUE: Enable the DC bias voltage on the input or bidirectional buffer driven by the top-level port.
FALSE: Disable DQS_BIAS on the buffer driven by the top-level port.
Note: When EQUALIZATION = EQ_NONE, the DQS_BIAS must be FALSE. Any other EQUALIZATION value (EQ_LEVEL1, EQ_LEVEL2...) can support either DQS_BIAS of TRUE or FALSE.

Syntax

Verilog Syntax

Assign the DQS_BIAS parameter on the top-level port driving the instantiated differential buffer immediately before the port declaration:

(* DQS_BIAS = "TRUE" *) input PORT;

Verilog Syntax Example:

The following example enables differential termination on the top-level port CLK_p driving the differential input buffer IBUFDS.

// Enables the DC bias voltage on the buffer driven by the specified port 
(* DQS_BIAS = "TRUE" *) input CLK_p;

VHDL Syntax

Assign the generic DQS_BIAS on the top-level port driving the instantiated differential buffer:

attribute DQS_BIAS : string;
attribute DQS_BIAS of port_name : signal is "TRUE";

VHDL Syntax Example:

The following example enables differential termination on the top-level port CLK_p driving the differential input buffer IBUFDS.

--Enables the DC bias voltage on the buffer driven by the specified port attribute DQS_BIAS of CLK_p : signal is "TRUE";

XDC Syntax

The DQS_BIAS attribute uses the following syntax in the XDC file:

set_property DQS_BIAS [TRUE | FALSE] [get_ports <port_name>]

Where <port_name> is an input or bidirectional top-level port.

XDC Syntax Example:

# Enable DQS_BIAS on the specified clk port 
set_property DQS_BIAS TRUE [get_ports clk]

Affected Steps

Synthesis
Simulation