The Vivado tool merges the drivers of all
logically-equivalent signals into single drivers when the
-merge_equivalent_drivers option is specified during logic
opt_design). Refer to Logic
Optimization in the
Vivado Design Suite User Guide:
Implementation (UG904) for
The EQUIVALENT_DRIVER_OPT cell property lets you control which equivalent nets and
drivers are merged or not when running
- Setting the EQUIVALENT_DRIVER_OPT property to MERGE on the original driver, and
its replicas, triggers the merge equivalent driver phase during
opt_design, and merges the logically equivalent drivers that have that property.
- Setting the EQUIVALENT_DRIVER_OPT property to KEEP on the original driver, and its replicas, prevents the merging of those specified drivers during the equivalent driver merging and the control set merging phase. This excludes the specified drivers, but otherwise runs equivalent driver merging on the rest of the design.
- Architecture Support
- All architectures.
- Applicable Objects
- Cells (
MERGE: Enable the equivalent driver merging optimization on the specified cells only.
KEEP: Disables the equivalent driver merging optimization on the specified cells, but otherwise merge the rest of the design.
- Verilog Syntax
- VHDL Syntax
- XDC Syntax
set_property EQUIVALENT_DRIVER_OPT < MERGE | KEEP > [get_cells <instance>]
XDC Syntax Example:
# Specifies to MERGE equivalent drivers on the specified cells set_property EQUIVALENT_DRIVER_OPT MERGE [get_cells U0/mem_reg_mux_sel_reg_0*]
- Opt Design