You can force the replication of a register or a LUT driving a net by adding the FORCE_MAX_FANOUT property to the net. The value of the FORCE_MAX_FANOUT specifies the maximum physical fanout the nets should have after the replication optimization. The physical fanout in this case refers to the actual site pin loads, not the logical loads. For example, if the replica drives multiple LUTRAM loads that are all grouped in the same slice, the combined fanout will be 1 for all of the LUTRAMs in the same slice. The FORCE_MAX_FANOUT forces the replication during physical synthesis regardless of the slack of the signal.
- Architecture Support
- All architectures.
- Applicable Objects
- Nets (
get_nets) directly connected to the output of a Register (FD, FDCE, FDPE, FDRE, FDSE) or LUT (LUT1, LUT2, LUT3, LUT4, LUT5, LUT6, LUT6_2)..
<Integer>: Specifies the maximum limit of fanout, after which the driver is replicated
- Verilog Syntax
- VHDL Syntax
- XDC Syntax
set_property FORCE_MAX_FANOUT <number> [get_nets <net_name>]
- Place Design