FSM_ENCODING controls how a state machine is encoded during synthesis.
As a default, the Vivado synthesis tool chooses an encoding protocol for state machines based on internal algorithms that determine the best solution for most designs. However, the FSM_ENCODING property lets you specify the state machine encoding of your choice.
- Architecture Support
- All architectures.
- Applicable Objects
- State machine registers.
AUTO: This is the default behavior when FSM_ENCODING is not specified. It allows the Vivado synthesis tool to determine the best state machine encoding method. In this case, the tool might use different encoding styles for different state machine registers in the same design.
NONE: This disables state machine encoding within the Vivado synthesis tool for the specified state machine registers. In this case the state machine is synthesized as logic.
- Verilog Syntax
(* fsm_encoding = "one_hot" *) reg [7:0] my_state;
- VHDL Syntax
type count_state is (zero, one, two, three, four, five, six, seven); signal my_state : count_state; attribute fsm_encoding : string; attribute fsm_encoding of my_state : signal is "sequential";
- XDC Syntax
- Not applicable