HW_SIO_GT - 2023.2 English

Vivado Design Suite Properties Reference Guide (UG912)
Document ID
UG912
Release Date
2023-11-01
Version
2023.2 English

Description

The customizable AMD LogiCORE™ IP Integrated Bit Error Ratio Tester (IBERT) core for AMD FPGAs is designed for evaluating and monitoring the Gigabit Transceivers (GTs). The IBERT core enables in-system serial I/O validation and debug, letting you measure and optimize the high-speed serial I/O links in your design. Refer to the Integrated Bit Error Ratio Tester 7 Series GTX Transceivers LogiCORE IP Product Guide (PG132) for more information.

Using the IBERT debug core you can configure and tune the GT transmitters and receivers through the Dynamic Reconfiguration Port (DRP) port of the GTX transceiver. This lets you change property settings on the GTs, as well as registers that control the values on the ports.

Related Objects

Figure 1. Hardware SIO GT Objects

HW_SIO_GT objects are associated with hw_server, hw_target, hw_device, hw_sio_gt,hw_sio_common, hw_sio_pll, hw_sio_tx, hw_sio_rx, or hw_sio_link objects. You can query the GT objects associated with these objects:

get_hw_sio_gts -of_objects [get_hw_sio_links]

You can also query the objects associated with hw_sio_gt objects:

get_hw_sio_gtgroups -of [get_hw_sio_gts *MGT_X0Y9]

Properties

You can use the report_property command to report the actual properties assigned to a specific HW_SIO_GT. Refer to the Vivado Design Suite Tcl Command Reference Guide (UG835) for more information.

The properties assigned to HW_SIO_GT objects include the following:

Property	Type	Read-only	Visible	Value
CLASS	string	true	true	hw_sio_gt
CPLLREFCLKSEL	enum	false	true	GTREFCLK0
CPLL_FBDIV	enum	false	true	1
CPLL_FBDIV_45	enum	false	true	4
CPLL_REFCLK_DIV	enum	false	true	1
DISPLAY_NAME	string	true	true	MGT_X0Y8
DRP.ALIGN_COMMA_DOUBLE	string	false	true	0
DRP.ALIGN_COMMA_ENABLE	string	false	true	07F
DRP.ALIGN_COMMA_WORD	string	false	true	1
DRP.ALIGN_MCOMMA_DET	string	false	true	1
DRP.ALIGN_MCOMMA_VALUE	string	false	true	283
DRP.ALIGN_PCOMMA_DET	string	false	true	1
DRP.ALIGN_PCOMMA_VALUE	string	false	true	17C
DRP.CBCC_DATA_SOURCE_SEL	string	false	true	1
DRP.CHAN_BOND_KEEP_ALIGN	string	false	true	0
DRP.CHAN_BOND_MAX_SKEW	string	false	true	7
DRP.CHAN_BOND_SEQ_1_1	string	false	true	17C
DRP.CHAN_BOND_SEQ_1_2	string	false	true	100
DRP.CHAN_BOND_SEQ_1_3	string	false	true	100
DRP.CHAN_BOND_SEQ_1_4	string	false	true	100
DRP.CHAN_BOND_SEQ_1_ENABLE	string	false	true	F
DRP.CHAN_BOND_SEQ_2_1	string	false	true	100
DRP.CHAN_BOND_SEQ_2_2	string	false	true	100
DRP.CHAN_BOND_SEQ_2_3	string	false	true	100
DRP.CHAN_BOND_SEQ_2_4	string	false	true	100
DRP.CHAN_BOND_SEQ_2_ENABLE	string	false	true	F
DRP.CHAN_BOND_SEQ_2_USE	string	false	true	0
DRP.CHAN_BOND_SEQ_LEN	string	false	true	0
DRP.CLK_CORRECT_USE	string	false	true	0
DRP.CLK_COR_KEEP_IDLE	string	false	true	0
DRP.CLK_COR_MAX_LAT	string	false	true	13
DRP.CLK_COR_MIN_LAT	string	false	true	0F
DRP.CLK_COR_PRECEDENCE	string	false	true	1
DRP.CLK_COR_REPEAT_WAIT	string	false	true	00
DRP.CLK_COR_SEQ_1_1	string	false	true	11C
DRP.CLK_COR_SEQ_1_2	string	false	true	100
DRP.CLK_COR_SEQ_1_3	string	false	true	100
DRP.CLK_COR_SEQ_1_4	string	false	true	100
DRP.CLK_COR_SEQ_1_ENABLE	string	false	true	F
DRP.CLK_COR_SEQ_2_1	string	false	true	100
DRP.CLK_COR_SEQ_2_2	string	false	true	100
DRP.CLK_COR_SEQ_2_3	string	false	true	100
DRP.CLK_COR_SEQ_2_4	string	false	true	100
DRP.CLK_COR_SEQ_2_ENABLE	string	false	true	F
DRP.CLK_COR_SEQ_2_USE	string	false	true	0
DRP.CLK_COR_SEQ_LEN	string	false	true	0
DRP.CPLL_CFG	string	false	true	BC07DC
DRP.CPLL_FBDIV	string	false	true	10
DRP.CPLL_FBDIV_45	string	false	true	0
DRP.CPLL_INIT_CFG	string	false	true	00001E
DRP.CPLL_LOCK_CFG	string	false	true	01C0
DRP.CPLL_REFCLK_DIV	string	false	true	10
DRP.DEC_MCOMMA_DETECT	string	false	true	0
DRP.DEC_PCOMMA_DETECT	string	false	true	0
DRP.DEC_VALID_COMMA_ONLY	string	false	true	0
DRP.DMONITOR_CFG	string	false	true	000A01
DRP.ES_CONTROL	string	false	true	00
DRP.ES_CONTROL_STATUS	string	false	true	0
DRP.ES_ERRDET_EN	string	false	true	0
DRP.ES_ERROR_COUNT	string	false	true	0000
DRP.ES_EYE_SCAN_EN	string	false	true	1
DRP.ES_HORZ_OFFSET	string	false	true	000
DRP.ES_PMA_CFG	string	false	true	000
DRP.ES_PRESCALE	string	false	true	00
DRP.ES_QUALIFIER	string	false	true	00000000000000000000
DRP.ES_QUAL_MASK	string	false	true	00000000000000000000
DRP.ES_RDATA	string	false	true	00000000000000000000
DRP.ES_SAMPLE_COUNT	string	false	true	0000
DRP.ES_SDATA	string	false	true	00000000000000000000
DRP.ES_SDATA_MASK	string	false	true	00000000000000000000
DRP.ES_UT_SIGN	string	false	true	0
DRP.ES_VERT_OFFSET	string	false	true	000
DRP.FTS_DESKEW_SEQ_ENABLE	string	false	true	F
DRP.FTS_LANE_DESKEW_CFG	string	false	true	F
DRP.FTS_LANE_DESKEW_EN	string	false	true	0
DRP.GEARBOX_MODE	string	false	true	0
DRP.OUTREFCLK_SEL_INV	string	false	true	3
DRP.PCS_PCIE_EN	string	false	true	0
DRP.PCS_RSVD_ATTR	string	false	true	000000000000
DRP.PD_TRANS_TIME_FROM_P2	string	false	true	03C
DRP.PD_TRANS_TIME_NONE_P2	string	false	true	3C
DRP.PD_TRANS_TIME_TO_P2	string	false	true	64
DRP.PMA_RSV	string	false	true	001E7080
DRP.PMA_RSV2	string	false	true	2070
DRP.PMA_RSV2_BIT4	string	false	true	1
DRP.PMA_RSV3	string	false	true	0
DRP.PMA_RSV4	string	false	true	00000000
DRP.RXBUFRESET_TIME	string	false	true	01
DRP.RXBUF_ADDR_MODE	string	false	true	1
DRP.RXBUF_EIDLE_HI_CNT	string	false	true	8
DRP.RXBUF_EIDLE_LO_CNT	string	false	true	0
DRP.RXBUF_EN	string	false	true	1
DRP.RXBUF_RESET_ON_CB_CHANGE	string	false	true	1
DRP.RXBUF_RESET_ON_COMMAALIGN	string	false	true	0
DRP.RXBUF_RESET_ON_EIDLE	string	false	true	0
DRP.RXBUF_RESET_ON_RATE_CHANGE	string	false	true	1
DRP.RXBUF_THRESH_OVFLW	string	false	true	3D
DRP.RXBUF_THRESH_OVRD	string	false	true	0
DRP.RXBUF_THRESH_UNDFLW	string	false	true	04
DRP.RXCDRFREQRESET_TIME	string	false	true	01
DRP.RXCDRPHRESET_TIME string	false	true	01
DRP.RXCDR_CFG	string	false	true	0B800023FF10200020
DRP.RXCDR_FR_RESET_ON_EIDLE	string	false	true	0
DRP.RXCDR_HOLD_DURING_EIDLE	string	false	true	0
DRP.RXCDR_LOCK_CFG	string	false	true	15
DRP.RXCDR_PH_RESET_ON_EIDLE	string	false	true	0
DRP.RXDFELPMRESET_TIME	string	false	true	0F
DRP.RXDLY_CFG	string	false	true	001F
DRP.RXDLY_LCFG	string	false	true	030
DRP.RXDLY_TAP_CFG	string	false	true	0000
DRP.RXGEARBOX_EN	string	false	true	0
DRP.RXISCANRESET_TIME	string	false	true	01
DRP.RXLPM_HF_CFG	string	false	true	00F0
DRP.RXLPM_LF_CFG	string	false	true	00F0
DRP.RXOOB_CFG	string	false	true	06
DRP.RXOUT_DIV	string	false	true	0
DRP.RXPCSRESET_TIME	string	false	true	01
DRP.RXPHDLY_CFG	string	false	true	084020
DRP.RXPH_CFG	string	false	true	000000
DRP.RXPH_MONITOR_SEL	string	false	true	00
DRP.RXPMARESET_TIME	string	false	true	03
DRP.RXPRBS_ERR_LOOPBACK	string	false	true	0
DRP.RXSLIDE_AUTO_WAIT	string	false	true	7
DRP.RXSLIDE_MODE	string	false	true	0
DRP.RX_BIAS_CFG	string	false	true	004
DRP.RX_BUFFER_CFG	string	false	true	00
DRP.RX_CLK25_DIV	string	false	true	04
DRP.RX_CLKMUX_PD	string	false	true	1
DRP.RX_CM_SEL	string	false	true	3
DRP.RX_CM_TRIM	string	false	true	4
DRP.RX_DATA_WIDTH	string	false	true	5
DRP.RX_DDI_SEL	string	false	true	00
DRP.RX_DEBUG_CFG	string	false	true	000
DRP.RX_DEFER_RESET_BUF_EN	string	false	true	1
DRP.RX_DFE_CTLE_STAGE1	string	false	true	8
DRP.RX_DFE_CTLE_STAGE2	string	false	true	3
DRP.RX_DFE_CTLE_STAGE3	string	false	true	0
DRP.RX_DFE_GAIN_CFG	string	false	true	020FEA
DRP.RX_DFE_H2_CFG	string	false	true	000
DRP.RX_DFE_H3_CFG	string	false	true	040
DRP.RX_DFE_H4_CFG	string	false	true	0F0
DRP.RX_DFE_H5_CFG	string	false	true	0E0
DRP.RX_DFE_KL_CFG	string	false	true	00FE
DRP.RX_DFE_KL_CFG2	string	false	true	3010D90C
DRP.RX_DFE_LPM_CFG	string	false	true	0954
DRP.RX_DFE_LPM_HOLD_DURING_EIDLE	string	false	true	0
DRP.RX_DFE_UT_CFG	string	false	true	11E00
DRP.RX_DFE_VP_CFG	string	false	true	03F03
DRP.RX_DFE_XYD_CFG	string	false	true	0000
DRP.RX_DISPERR_SEQ_MATCH	string	false	true	1
DRP.RX_INT_DATAWIDTH	string	false	true	1
DRP.RX_OS_CFG	string	false	true	0080
DRP.RX_SIG_VALID_DLY	string	false	true	09
DRP.RX_XCLK_SEL	string	false	true	0
DRP.SAS_MAX_COM	string	false	true	40
DRP.SAS_MIN_COM	string	false	true	24
DRP.SATA_BURST_SEQ_LEN	string	false	true	F
DRP.SATA_BURST_VAL	string	false	true	4
DRP.SATA_CPLL_CFG	string	false	true	0
DRP.SATA_EIDLE_VAL	string	false	true	4	
DRP.SATA_MAX_BURST	string	false	true	08	
DRP.SATA_MAX_INIT	string	false	true	15	
DRP.SATA_MAX_WAKE	string	false	true	07	
DRP.SATA_MIN_BURST	string	false	true	04	
DRP.SATA_MIN_INIT	string	false	true	0C	
DRP.SATA_MIN_WAKE	string	false	true	04	
DRP.SHOW_REALIGN_COMMA	string	false	true	1	
DRP.TERM_RCAL_CFG	string	false	true	10	
DRP.TERM_RCAL_OVRD	string	false	true	0	
DRP.TRANS_TIME_RATE	string	false	true	0E	
DRP.TST_RSV	string	false	true	00000000	
DRP.TXBUF_EN	string	false	true	1	
DRP.TXBUF_RESET_ON_RATE_CHANGE	string	false	true	0	
DRP.TXDLY_CFG	string	false	true	001F	
DRP.TXDLY_LCFG	string	false	true	030	
DRP.TXDLY_TAP_CFG	string	false	true	0000	
DRP.TXGEARBOX_EN	string	false	true	0	
DRP.TXOUT_DIV	string	false	true	0	
DRP.TXPCSRESET_TIME	string	false	true	01	
DRP.TXPHDLY_CFG	string	false	true	084020	
DRP.TXPH_CFG	string	false	true	0780	
DRP.TXPH_MONITOR_SEL	string	false	true	00	
DRP.TXPMARESET_TIME	string	false	true	01	
DRP.TX_CLK25_DIV	string	false	true	04	
DRP.TX_CLKMUX_PD	string	false	true	1	
DRP.TX_DATA_WIDTH	string	false	true	5	
DRP.TX_DEEMPH0	string	false	true	00	
DRP.TX_DEEMPH1	string	false	true	00	
DRP.TX_DRIVE_MODE	string	false	true	00	
DRP.TX_EIDLE_ASSERT_DELAY	string	false	true	6	
DRP.TX_EIDLE_DEASSERT_DELAY	string	false	true	4	
DRP.TX_INT_DATAWIDTH	string	false	true	1	
DRP.TX_LOOPBACK_DRIVE_HIZ	string	false	true	0	
DRP.TX_MAINCURSOR_SEL	string	false	true	0	
DRP.TX_MARGIN_FULL_0	string	false	true	4E	
DRP.TX_MARGIN_FULL_1	string	false	true	49	
DRP.TX_MARGIN_FULL_2	string	false	true	45	
DRP.TX_MARGIN_FULL_3	string	false	true	42	
DRP.TX_MARGIN_FULL_4	string	false	true	40	
DRP.TX_MARGIN_LOW_0	string	false	true	46	
DRP.TX_MARGIN_LOW_1	string	false	true	44	
DRP.TX_MARGIN_LOW_2	string	false	true	42	
DRP.TX_MARGIN_LOW_3	string	false	true	40	
DRP.TX_MARGIN_LOW_4	string	false	true	40	
DRP.TX_PREDRIVER_MODE	string	false	true	0	
DRP.TX_QPI_STATUS_EN	string	false	true	0	
DRP.TX_RXDETECT_CFG	string	false	true	1832	
DRP.TX_RXDETECT_REF	string	false	true	4	
DRP.TX_XCLK_SEL	string	false	true	0	
DRP.UCODEER_CLR	string	false	true	0	
ES_HORZ_MIN_MAX	string	false	true	32	
GT_TYPE	string	true	true	7 Series	GTX
LINE_RATE	string	false	true	0.000	
LOGIC.DEBUG_CLOCKS	string	false	true	0	
LOGIC.ERRBIT_COUNT	string	false	true	000000000000
LOGIC.ERR_INJECT_CTRL	string	false	true	0
LOGIC.FRAME_LEN	string	false	true	0000
LOGIC.GT_SOURCES_SYSCLK	string	false	true	0
LOGIC.IDLE_DETECTED	string	false	true	0
LOGIC.IFG_LEN	string	false	true	00
LOGIC.LINK	string	false	true	0
LOGIC.MAX_LINERATE	string	false	true	0001DCD65000
LOGIC.MAX_REFCLK_FREQ	string	false	true	07735940
LOGIC.MGT_COORDINATE	string	false	true	0008
LOGIC.MGT_ERRCNT_RESET_CTRL	string	false	true	0
LOGIC.MGT_ERRCNT_RESET_STAT	string	false	true	0
LOGIC.MGT_NUMBER	string	false	true	0075
LOGIC.MGT_RESET_CTRL	string	false	true	0
LOGIC.MGT_RESET_STAT	string	false	true	0
LOGIC.PROTOCOL_ENUM	string	false	true	0000
LOGIC.RXPAT_ID	string	false	true	1
LOGIC.RXRECCLK_FREQ_CNT	string	false	true	0000
LOGIC.RXRECCLK_FREQ_TUNE	string	false	true	4000
LOGIC.RXUSRCLK2_FREQ_CNT	string	false	true	0000
LOGIC.RXUSRCLK2_FREQ_TUNE	string	false	true	4000
LOGIC.RXUSRCLK_FREQ_CNT	string	false	true	0000
LOGIC.RXUSRCLK_FREQ_TUNE	string	false	true	4000
LOGIC.RXWORD_COUNT	string	false	true	000000000000
LOGIC.RX_DCM_LOCK	string	false	true	1
LOGIC.RX_DCM_RESET_CTRL	string	false	true	0
LOGIC.RX_DCM_RESET_STAT	string	false	true	0
LOGIC.RX_FRAMED	string	false	true	0
LOGIC.SILICON_VERSION	string	false	true	0300
LOGIC.TIMER	string	false	true	009736E7B9BC
LOGIC.TXOUTCLK_FREQ_CNT	string	false	true	0000
LOGIC.TXOUTCLK_FREQ_TUNE	string	false	true	4000
LOGIC.TXPAT_ID	string	false	true	1
LOGIC.TXUSRCLK2_FREQ_CNT	string	false	true	0000
LOGIC.TXUSRCLK2_FREQ_TUNE	string	false	true	4000
LOGIC.TXUSRCLK_FREQ_CNT	string	false	true	0000
LOGIC.TXUSRCLK_FREQ_TUNE	string	false	true	4000
LOGIC.TX_DCM_LOCK	string	false	true	1
LOGIC.TX_DCM_RESET_CTRL	string	false	true	0
LOGIC.TX_DCM_RESET_STAT	string	false	true	1
LOGIC.TX_FRAMED	string	false	true	0
LOOPBACK	enum	false	true	None
NAME	string	true	true	
localhost/xilinx_tcf/Digilent/210203327463A/0_1/IBERT/Quad_117/MGT_X0Y8 PARENT	string	true	true localhost/xilinx_tcf/Digilent/210203327463A/0_1/IBERT
PLL_STATUS	string	false	true	LOCKED
PORT.CFGRESET	string	false	true	0
PORT.CLKRSVD	string	false	true	0
PORT.CPLLFBCLKLOST	string	false	true	0
PORT.CPLLLOCK	string	false	true	1
PORT.CPLLLOCKDETCLK	string	false	true	0
PORT.CPLLLOCKEN	string	false	true	1
PORT.CPLLPD	string	false	true	0
PORT.CPLLREFCLKLOST	string	false	true	0
PORT.CPLLREFCLKSEL	string	false	true	1
PORT.CPLLRESET	string	false	true	0
PORT.DMONITOROUT	string	false	true	1F
PORT.EYESCANDATAERROR	string	false	true	0
PORT.EYESCANMODE	string	false	true	0
PORT.EYESCANRESET	string	false	true	0
PORT.EYESCANTRIGGER	string	false	true	0
PORT.GTREFCLKMONITOR	string	false	true	1
LOGIC.IDLE_DETECTED	string	false	true	0
LOGIC.IFG_LEN	string	false	true	00
LOGIC.LINK	string	false	true	0
LOGIC.MAX_LINERATE	string	false	true	0001DCD65000
LOGIC.MAX_REFCLK_FREQ	string	false	true	07735940
LOGIC.MGT_COORDINATE	string	false	true	0008
LOGIC.MGT_ERRCNT_RESET_CTRL	string	false	true	0
LOGIC.MGT_ERRCNT_RESET_STAT	string	false	true	0
LOGIC.MGT_NUMBER	string	false	true	0075
LOGIC.MGT_RESET_CTRL	string	false	true	0
LOGIC.MGT_RESET_STAT	string	false	true	0
LOGIC.PROTOCOL_ENUM	string	false	true	0000
LOGIC.RXPAT_ID	string	false	true	1
LOGIC.RXRECCLK_FREQ_CNT	string	false	true	0000
LOGIC.RXRECCLK_FREQ_TUNE	string	false	true	4000
LOGIC.RXUSRCLK2_FREQ_CNT	string	false	true	0000
LOGIC.RXUSRCLK2_FREQ_TUNE	string	false	true	4000
LOGIC.RXUSRCLK_FREQ_CNT	string	false	true	0000
LOGIC.RXUSRCLK_FREQ_TUNE	string	false	true	4000
LOGIC.RXWORD_COUNT	string	false	true	000000000000
LOGIC.RX_DCM_LOCK	string	false	true	1
LOGIC.RX_DCM_RESET_CTRL	string	false	true	0
LOGIC.RX_DCM_RESET_STAT	string	false	true	0
LOGIC.RX_FRAMED	string	false	true	0
LOGIC.SILICON_VERSION	string	false	true	0300
LOGIC.TIMER	string	false	true	009736E7B9BC
LOGIC.TXOUTCLK_FREQ_CNT	string	false	true	0000
LOGIC.TXOUTCLK_FREQ_TUNE	string	false	true	4000
LOGIC.TXPAT_ID	string	false	true	1
LOGIC.TXUSRCLK2_FREQ_CNT	string	false	true	0000
LOGIC.TXUSRCLK2_FREQ_TUNE	string	false	true	4000
LOGIC.TXUSRCLK_FREQ_CNT	string	false	true	0000
LOGIC.TXUSRCLK_FREQ_TUNE	string	false	true	4000
LOGIC.TX_DCM_LOCK	string	false	true	1
LOGIC.TX_DCM_RESET_CTRL	string	false	true	0
LOGIC.TX_DCM_RESET_STAT	string	false	true	1
LOGIC.TX_FRAMED	string	false	true	0
LOOPBACK	enum	false	true	None
NAME	string	true	true	
localhost/xilinx_tcf/Digilent/210203327463A/0_1/IBERT/Quad_117/MGT_X0Y8 PARENT	string	true	true localhost/xilinx_tcf/Digilent/210203327463A/0_1/IBERT
PLL_STATUS	string	false	true	LOCKED
PORT.CFGRESET	string	false	true	0
PORT.CLKRSVD	string	false	true	0
PORT.CPLLFBCLKLOST	string	false	true	0
PORT.CPLLLOCK	string	false	true	1
PORT.CPLLLOCKDETCLK	string	false	true	0
PORT.CPLLLOCKEN	string	false	true	1
PORT.CPLLPD	string	false	true	0
PORT.CPLLREFCLKLOST	string	false	true	0
PORT.CPLLREFCLKSEL	string	false	true	1
PORT.CPLLRESET	string	false	true	0
PORT.DMONITOROUT	string	false	true	1F
PORT.EYESCANDATAERROR	string	false	true	0
PORT.EYESCANMODE	string	false	true	0
PORT.EYESCANRESET	string	false	true	0
PORT.EYESCANTRIGGER	string	false	true	0
PORT.GTREFCLKMONITOR	string	false	true	1
PORT.GTRESETSEL	string	false	true	0
PORT.GTRSVD	string	false	true	0000
PORT.GTRXRESET	string	false	true	0
PORT.GTTXRESET	string	false	true	0
PORT.LOOPBACK	string	false	true	0
PORT.PCSRSVDIN	string	false	true	0000
PORT.PCSRSVDIN2	string	false	true	00
PORT.PCSRSVDOUT	string	false	true	01F3
PORT.PHYSTATUS	string	false	true	1
PORT.PMARSVDIN	string	false	true	00
PORT.PMARSVDIN2	string	false	true	00
PORT.RESETOVRD	string	false	true	0
PORT.RX8B10BEN	string	false	true	0
PORT.RXBUFRESET	string	false	true	0
PORT.RXBUFSTATUS	string	false	true	0
PORT.RXBYTEISALIGNED	string	false	true	0
PORT.RXBYTEREALIGN	string	false	true	0
PORT.RXCDRFREQRESET	string	false	true	0
PORT.RXCDRHOLD	string	false	true	0
PORT.RXCDRLOCK	string	false	true	0
PORT.RXCDROVRDEN	string	false	true	0
PORT.RXCDRRESET	string	false	true	0
PORT.RXCDRRESETRSV	string	false	true	0
PORT.RXCHANBONDSEQ	string	false	true	0
PORT.RXCHANISALIGNED	string	false	true	0
PORT.RXCHANREALIGN	string	false	true	0
PORT.RXCHARISCOMMA	string	false	true	00
PORT.RXCHARISK	string	false	true	00
PORT.RXCHBONDEN	string	false	true	0
PORT.RXCHBONDI	string	false	true	10
PORT.RXCHBONDLEVEL	string	false	true	0
PORT.RXCHBONDMASTER	string	false	true	0
PORT.RXCHBONDO	string	false	true	00
PORT.RXCHBONDSLAVE	string	false	true	0
PORT.RXCLKCORCNT	string	false	true	0
PORT.RXCOMINITDET	string	false	true	0
PORT.RXCOMMADET	string	false	true	0
PORT.RXCOMMADETEN	string	false	true	0
PORT.RXCOMSASDET	string	false	true	0
PORT.RXCOMWAKEDET	string	false	true	0
PORT.RXDATAVALID	string	false	true	0
PORT.RXDDIEN	string	false	true	0
PORT.RXDFEAGCHOLD	string	false	true	0
PORT.RXDFEAGCOVRDEN	string	false	true	0
PORT.RXDFECM1EN	string	false	true	0
PORT.RXDFELFHOLD	string	false	true	0
PORT.RXDFELFOVRDEN	string	false	true	0
PORT.RXDFELPMRESET	string	false	true	0
PORT.RXDFETAP2HOLD	string	false	true	0
PORT.RXDFETAP2OVRDEN	string	false	true	0
PORT.RXDFETAP3HOLD	string	false	true	0
PORT.RXDFETAP3OVRDEN	string	false	true	0
PORT.RXDFETAP4HOLD	string	false	true	0
PORT.RXDFETAP4OVRDEN	string	false	true	0
PORT.RXDFETAP5HOLD	string	false	true	0
PORT.RXDFETAP5OVRDEN	string	false	true	0
PORT.RXDFEUTHOLD	string	false	true	0
PORT.RXDFEUTOVRDEN	string	false	true	0
PORT.RXDFEVPHOLD	string	false	true	0
PORT.RXDFEVPOVRDEN	string	false	true	0
PORT.RXDFEVSEN	string	false	true	0
PORT.RXDFEXYDEN	string	false	true	0
PORT.RXDFEXYDHOLD	string	false	true	0
PORT.RXDFEXYDOVRDEN	string	false	true	0
PORT.RXDISPERR	string	false	true	00
PORT.RXDLYBYPASS	string	false	true	1
PORT.RXDLYEN	string	false	true	0
PORT.RXDLYOVRDEN	string	false	true	0
PORT.RXDLYSRESET	string	false	true	0
PORT.RXDLYSRESETDONE	string	false	true	0
PORT.RXELECIDLE	string	false	true	1
PORT.RXELECIDLEMODE	string	false	true	0
PORT.RXGEARBOXSLIP	string	false	true	0
PORT.RXHEADER	string	false	true	0
PORT.RXHEADERVALID	string	false	true	0
PORT.RXLPMEN	string	false	true	0
PORT.RXLPMHFHOLD	string	false	true	0
PORT.RXLPMHFOVRDEN	string	false	true	0
PORT.RXLPMLFHOLD	string	false	true	0
PORT.RXLPMLFKLOVRDEN	string	false	true	0
PORT.RXMCOMMAALIGNEN	string	false	true	0
PORT.RXMONITOROUT	string	false	true	7F
PORT.RXMONITORSEL	string	false	true	0
PORT.RXNOTINTABLE	string	false	true	FF
PORT.RXOOBRESET	string	false	true	0
PORT.RXOSHOLD	string	false	true	0
PORT.RXOSOVRDEN	string	false	true	0
PORT.RXOUTCLKFABRIC	string	false	true	0
PORT.RXOUTCLKPCS	string	false	true	0
PORT.RXOUTCLKSEL	string	false	true	1
PORT.RXPCOMMAALIGNEN	string	false	true	0
PORT.RXPCSRESET	string	false	true	0
PORT.RXPD	string	false	true	0
PORT.RXPHALIGN	string	false	true	0
PORT.RXPHALIGNDONE	string	false	true	0
PORT.RXPHALIGNEN	string	false	true	0
PORT.RXPHDLYPD	string	false	true	0
PORT.RXPHDLYRESET	string	false	true	0
PORT.RXPHMONITOR	string	false	true	00
PORT.RXPHOVRDEN	string	false	true	0
PORT.RXPHSLIPMONITOR	string	false	true	04
PORT.RXPMARESET	string	false	true	0
PORT.RXPOLARITY	string	false	true	0
PORT.RXPRBSCNTRESET	string	false	true	0
PORT.RXPRBSERR	string	false	true	0
PORT.RXPRBSSEL	string	false	true	0
PORT.RXQPIEN	string	false	true	0
PORT.RXQPISENN	string	false	true	0
PORT.RXQPISENP	string	false	true	0
PORT.RXRATE	string	false	true	0
PORT.RXRATEDONE	string	false	true	0
PORT.RXRESETDONE	string	false	true	0
PORT.RXSLIDE	string	false	true	0
PORT.RXSTARTOFSEQ	string	false	true	0
PORT.RXSTATUS	string	false	true	0
PORT.RXSYSCLKSEL	string	false	true	3
PORT.RXUSERRDY	string	false	true	1
PORT.RXVALID	string	false	true	0
PORT.SETERRSTATUS	string	false	true	0
PORT.TSTIN	string	false	true	FFFFF
PORT.TSTOUT	string	false	true	000
PORT.TX8B10BBYPASS	string	false	true	FF
PORT.TX8B10BEN	string	false	true	0
PORT.TXBUFDIFFCTRL	string	false	true	4
PORT.TXBUFSTATUS	string	false	true	0
PORT.TXCHARDISPMODE	string	false	true	00
PORT.TXCHARDISPVAL	string	false	true	00
PORT.TXCHARISK	string	false	true	00
PORT.TXCOMFINISH	string	false	true	0
PORT.TXCOMINIT	string	false	true	0
PORT.TXCOMSAS	string	false	true	0
PORT.TXCOMWAKE	string	false	true	0
PORT.TXDEEMPH	string	false	true	0
PORT.TXDETECTRX	string	false	true	0
PORT.TXDIFFCTRL	string	false	true	C
PORT.TXDIFFPD	string	false	true	0
PORT.TXDLYBYPASS	string	false	true	1
PORT.TXDLYEN	string	false	true	0
PORT.TXDLYHOLD	string	false	true	0
PORT.TXDLYOVRDEN	string	false	true	0
PORT.TXDLYSRESET	string	false	true	0
PORT.TXDLYSRESETDONE	string	false	true	0
PORT.TXDLYUPDOWN	string	false	true	0
PORT.TXELECIDLE	string	false	true	0
PORT.TXGEARBOXREADY	string	false	true	0
PORT.TXHEADER	string	false	true	0
PORT.TXINHIBIT	string	false	true	0
PORT.TXMAINCURSOR	string	false	true	00
PORT.TXMARGIN	string	false	true	0
PORT.TXOUTCLKFABRIC	string	false	true	1
PORT.TXOUTCLKPCS	string	false	true	0
PORT.TXOUTCLKSEL	string	false	true	2
PORT.TXPCSRESET	string	false	true	0
PORT.TXPD	string	false	true	0
PORT.TXPDELECIDLEMODE	string	false	true	0
PORT.TXPHALIGN	string	false	true	0
PORT.TXPHALIGNDONE	string	false	true	0
PORT.TXPHALIGNEN	string	false	true	0
PORT.TXPHDLYPD	string	false	true	0
PORT.TXPHDLYRESET	string	false	true	0
PORT.TXPHDLYTSTCLK	string	false	true	0
PORT.TXPHINIT	string	false	true	0
PORT.TXPHINITDONE	string	false	true	0
PORT.TXPHOVRDEN	string	false	true	0
PORT.TXPISOPD	string	false	true	0
PORT.TXPMARESET	string	false	true	0
PORT.TXPOLARITY	string	false	true	0
PORT.TXPOSTCURSOR	string	false	true	03
PORT.TXPOSTCURSORINV	string	false	true	0
PORT.TXPRBSFORCEERR	string	false	true	0
PORT.TXPRBSSEL	string	false	true	0
PORT.TXPRECURSOR	string	false	true	07
PORT.TXPRECURSORINV	string	false	true	0
PORT.TXQPIBIASEN	string	false	true	0
PORT.TXQPISENN	string	false	true	0
PORT.TXQPISENP	string	false	true	0
PORT.TXQPISTRONGPDOWN	string	false	true	0
PORT.TXQPIWEAKPUP	string	false	true	0
PORT.TXRATE	string	false	true	0
PORT.TXRATEDONE	string	false	true	0
PORT.TXRESETDONE	string	false	true	0
PORT.TXSEQUENCE	string	false	true	00
PORT.TXSTARTSEQ	string	false	true	0
PORT.TXSWING	string	false	true	0
PORT.TXSYSCLKSEL	string	false	true	3
PORT.TXUSERRDY	string	false	true	1
RXDFEENABLED	enum	false	true	1
RXOUTCLKSEL	enum	false	true	RXOUTCLKPCS
RXOUT_DIV	enum	false	true	1
RXPLL	enum	false	true	QPLL
RXRATE	enum	false	true	Use RX_OUT_DIV
RXTERM	enum	false	true	900 mV
RXTERMMODE	enum	false	true	Programmable
RXUSRCLK2_FREQ	string	false	true	0.048828
RXUSRCLK_FREQ	string	false	true	0.048828
RX_BER	string	false	true	inf
RX_DATA_WIDTH	enum	false	true	40
RX_DFE_CTLE	enum	false	true	
RX_INTERNAL_DATAPATH	enum	false	true	4-byte
RX_PATTERN	enum	false	true	PRBS 7-bit
RX_RECEIVED_BIT_COUNT	string	false	true	0
STATUS	string	false	true	NO LINK
SYSCLK_FREQ	string	false	true	100.000000
TXDIFFSWING	enum	false	true	1.018 V (1100)
TXOUTCLKSEL	enum	false	true	TXOUTCLKPMA
TXOUT_DIV	enum	false	true	1
TXPLL	enum	false	true	QPLL
TXPOST	enum	false	true	0.68 dB (00011)
TXPRE	enum	false	true	1.67 dB (00111)
TXRATE	enum	false	true	Use TXOUT_DIV
TXUSRCLK2_FREQ	string	false	true	0.048828
TXUSRCLK_FREQ	string	false	true	0.048828
TX_DATA_WIDTH	enum	false	true	40
TX_INTERNAL_DATAPATH	enum	false	true	4-byte
TX_PATTERN	enum	false	true	PRBS 7-bit

To report the properties for the HW_SIO_GT object, you can copy and paste the following command into the Vivado Design Suite Tcl shell or Tcl Console:

report_property -all [lindex [get_hw_sio_gts] 0]