KEEP_HIERARCHY - 2023.2 English

KEEP_HIERARCHY directs the tool to retain a user hierarchy so that optimization does not occur across its boundary. While this can assist floorplanning, analysis, and debugging, it can inhibit optimization, resulting in a larger, slower design.

KEEP_HIERARCHY is used to prevent optimizations along the hierarchy boundaries. The Vivado synthesis tool attempts to keep the same general hierarchies specified in the RTL, but to improve quality of results (QoR), it can flatten or modify them.

If KEEP_HIERARCHY is placed on the instance, the synthesis tool keeps the boundary on that level static. This can affect QoR and also should not be used on modules that describe the control logic of 3-state outputs and I/O buffers. The KEEP_HIERARCHY can be placed in the module or architecture level or the instance.

Architecture Support

All architectures.

Applicable Objects

Hierarchical modules (get_cells)

Values

• TRUE: Preserves the hierarchy by not allowing optimization across the hierarchy boundary.
• FALSE: Allows optimization across the hierarchy (default).

Syntax

Verilog Syntax

Place the Verilog attribute immediately before the user hierarchy instantiation:

(* KEEP_HIERARCHY = "{TRUE|FALSE}" *)

Verilog Syntax Example:

// Preserve the hierarchy of instance CLK1_rst_sync (* KEEP_HIERARCHY = "TRUE" *) reset_sync #(
.STAGES(5)
) CLK1_rst_sync (
.RST_IN(RST | ~LOCKED),
.CLK(clk1_100mhz),
.RST_OUT(rst_clk1)
);

On Module:

(* keep_hierarchy = "yes" *) module bottom (in1, in2, in3, in4, out1, out2);

On Instance:

(* keep_hierarchy = "yes" *)bottom u0 (.in1(in1), .in2(in2), .out1(temp1));

VHDL Syntax

Declare the VHDL attribute as follows:

attribute KEEP_HIERARCHY : string;

Specify the VHDL attribute as follows:

attribute KEEP_HIERACHRY of name: label is "{TRUE|FALSE}";

Where name is the instance name of a user defined instance.

VHDL Syntax Example:

attribute KEEP_HIERARCHY : string;
-- Preserve the hierarchy of instance CLK1_rst_sync attribute KEEP_HIERARCHY of CLK1_rst_sync: label is "TRUE";
…
CLK1_rst_sync : reset_sync PORT MAP (
RST_IN => RST_LOCKED,
CLK => clk1_100mhz, RST_OUT	=> rst_clk1
);

On a module:

attribute keep_hierarchy : string;
attribute keep_hierarchy of beh : architecture is "yes";

On an instance:

attribute keep_hierarchy : string;
attribute keep_hierarchy of u0 : label is "yes";

XDC Syntax

set_property KEEP_HIERARCHY {TRUE|FALSE} [get_cells instance_name]

Where instance_name is a hierarchical module.

XDC Syntax Example:

# Preserve the hierarchy of instance CLK1_rst_sync 
set_property KEEP_HIERARCHY TRUE [get_cells CLK1_rst_sync]

Affected Steps

• Synthesis