Often, users want IP that was validated in the previous release to be not upgraded. It is possible to selectively upgrade some IP within a block design. There are some limitations to this flow that a user must understand. This section describes the process to selectively upgrade IP, the requirements the consequences of doing so, and the limitations to this flow.
The LOCK_UPGRADE property lets you specify certain cells or IP in a block design to prevent those cells or IP from being upgraded.
It might be that you have validated the IP in a prior release, and you have all of the required output products, and you want to work with that content without upgrading to the latest version of the IP. With the LOCK_UPGRADE property you can select specific IP to be excluded from the upgrade process.
However, there are some limitations to this flow that you should understand. Refer to the section on “Selectively Upgrading IP in Block Designs” in Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) to learn the requirements of this flow, and to “Limitations of Selectively Upgrading IP in Block Designs” to learn the limitations.
- Architecture Support
- All architectures.
- Applicable Objects
- Block diagram cells (
TRUE| 1: Lock the specified block design cell or IP to prevent it from being upgraded as part of the rest of the block design.
FALSE| 0: Do not lock the block design cell to prevent upgrading (default).
- Verilog Syntax
- VHDL Syntax
- XDC Syntax
set_property LOCK_UPGRADE <TRUE | FALSE> [get_bd_cells cell_name]
set_property LOCK_UPGRADE 1 [get_bd_cells /axi_ethernet_0]
- IP upgrade