On UltraScale devices, the LVDS_PRE_EMPHASIS property is used to improve signal integrity of high-frequency signals that suffer high-frequency losses through the transmission line.
LVDS Transmitter pre-emphasis provides a voltage boost (gain) at the signal transitions to compensate for transmission-line losses on the drivers implementing certain I/O standards. Pre-emphasis for DDR4 HP I/O banks and LVDS TX HP/HR I/O banks is available to reduce inter-symbol interference and to minimize the effects of transmission line loss.
The pre-emphasis at the transmitter is also a key to the signal integrity at the receiver. Pre-emphasis increases the signal edge rate, which also increases the crosstalk on neighboring signals.
Because the impact of pre-emphasis is dependent on the transmission line characteristics, simulation is required to ensure the impact is minimal. Over emphasis of the signal can further degrade the signal quality instead of improving it.
The use of
LVDS_PRE_EMPHASIS=FALSE results in two different I/O standards,
that cannot be placed together into a single I/O bank. This can result in the
following placement design rule violation found during
ERROR: [DRC 23-20] Rule violation (DIFFSTDLIMIT-1) Too many true differential output standards in bank.
- Architecture Support
- UltraScale devices.
- Applicable Objects
- Ports (
TRUE: Enable pre-emphasis for differential inputs and bidirectional buffers implementing the LVDS I/O standard. When set to TRUE, the ENABLE_PRE_EMPHASIS property on the TX_BITSLICE must also be set to TRUE.
FALSE: Do not enable pre-emphasis (default).
- Verilog Syntax
- VHDL Syntax
- XDC Syntax
The LVDS_PRE_EMPHASIS attribute uses the following syntax in the XDC file:
set_property LVDS_PRE_EMPHASIS <TRUE|FALSE> [get_ports port_name]
set_propertyLVDS_PRE_EMPHASIS enables pre-emphasis at the transmitter.
port_nameis an output or bidirectional port connected to a differential output buffer.