MARK_DEBUG - 2023.2 English

Use MARK_DEBUG to specify that a net should be preserved during synthesis for hardware debug. This will prevent optimization that could otherwise eliminate or change the name of the specified signal. The MARK_DEBUG property preserves the signal to provide an easy means of observing the values on this signal during hardware debug.

MARK_DEBUG prevents optimizations, much like the DONT_TOUCH, KEEP, or KEEP_HIERARCHY properties. MARK_DEBUG can also affect optimization of hierarchical modules connected to signals that are marked for debug. While this can assist analysis and debugging, reduced optimization can result in a larger, slower design. For this reason, AMD recommends that you use MARK_DEBUG sparingly, particularly on timing critical areas of the design, and to attach to synchronous points in the design only to limit the increased area and power, and the impact on timing closure.

Often, you identify nets for debugging through the pins of hierarchies or cells; however, the MARK_DEBUG property must be assigned to nets. Therefore, it is recommended that you assign MARK_DEBUG using both the get_nets and the get_pins commands:

set_property MARK_DEBUG true [get_nets –of [get_pins hier1/hier2/<flop_name>/Q]]

This ensures that the MARK_DEBUG property is assigned to the net connected to the specified pin regardless of how the net is named or renamed.

Architecture Support

All architectures.

Applicable Objects

Nets (get_nets): Any net accessible to the internal array.

Note: Some nets can have dedicated connectivity or other aspects that prohibit visibility for debug purposes.

Values

• TRUE: Preserve the signal for use during debug.
• FALSE: Do not preserve the signal (default).

Syntax

Verilog Syntax

To set this attribute, place the proper Verilog attribute syntax before the top-level output port declaration:

(* MARK_DEBUG = "{TRUE|FALSE}" *)

Verilog Syntax Example

// Marks an internal wire for debug in Vivado hardware manager 
(* MARK_DEBUG = "TRUE" *) wire debug_wire,

VHDL Syntax

Declare the VHDL attribute as follows:

attribute MARK_DEBUG : string;

Specify the VHDL attribute as follows:

attribute MARK_DEBUG of signal_name : signal is “{TRUE|FALSE}”;

Where signal_name is an internal signal.

VHDL Syntax Example:

signal debug_wire : std_logic; 
attribute MARK_DEBUG : string;
-- Marks an internal wire for debug in Vivado hardware manager 
attribute MARK_DEBUG of debug_wire : signal is “TRUE”;

XDC Syntax

set_property MARK_DEBUG value [get_nets <net_name>]

Where <net_name> is a signal name.

XDC Syntax Example:

# Marks an internal wire for debug
set_property MARK_DEBUG TRUE [get_nets debug_wire]

Affected Steps

• Synthesis
• Opt Design
• Place Design
• Vivado hardware manager