ODT - 2023.2 English

Vivado Design Suite Properties Reference Guide (UG912)
Document ID
UG912
Release Date
2023-11-01
Version
2023.2 English

The On-Die Termination (ODT) property is used to define the value of the on-die termination for both digitally controlled impedance (DCI) and non-DCI versions of the I/O standards supported. The advantage of using ODT over external resistors is that signal integrity is improved by completely removing the stub at the receiver.

Important: For 7 series FPGAs, use IN_TERM instead of ODT to specify uncalibrated termination.

ODT supports split or single termination on the inputs of the HSTL, SSTL, POD, and HSUL standards. The VCCO of the I/O bank must be connected to the appropriate voltage level for the ODT attribute to perform as expected. Refer to the UltraScale Architecture SelectIO Resources User Guide (UG571) for the VCCO levels required for specific I/O standards.

For the I/O standards that support parallel termination, DCI creates a Thevenin equivalent, or split-termination resistance to the VCCO /2 voltage level. For POD and HSUL standards, DCI supports a single-termination to the VCCO voltage level. The exact value of the termination resistors is determined by the ODT value. Possible ODT values for split-termination DCI are RTT_40, RTT_48, RTT_60, or RTT_NONE.

Note: DCI is only available in high-performance (HP) I/O banks. High-range (HR) I/O banks do not support DCI.

Both HR and HP I/O banks have an optional uncalibrated on-chip split-termination feature that creates a Thevenin equivalent circuit using two internal resistors of twice the target resistance value for HSTL and SSTL standards. They also provide an un-calibrated on-chip single-termination feature for POD and HSUL I/O standards. The termination is present constantly on inputs, and is present on bidirectional ports whenever the output buffer is 3-stated. The use of a DCI-based I/O standard determines whether the DCI or un-calibrated termination is invoked in a design. In both DCI and un-calibrated I/O standards, the values of the termination resistors are determined by the ODT attribute.

While the 3-state split-termination DCI is calibrated against external reference resistors on the VRN and VRP pins, the ODT property invokes an uncalibrated split-termination option using internal resistors that have no calibration to compensate for temperature, process, or voltage variations.

Architecture Support
UltraScale devices.
Applicable Objects
Ports (get_ports): Connected to input and bidirectional buffers.
Values
  • RTT_40
  • RTT_48
  • RTT_60
  • RTT_120
  • RTT_240
  • RTT_NONE
    Note: Not all values are allowed for all applicable I/O standards and configurations.

Syntax

Verilog Syntax

Not applicable

VHDL Syntax

Not applicable

XDC Syntax

The ODT attribute uses the following syntax in the XDC file:

set_property ODT <VALUE> [get_ports port_name]

Where:

  • set_property ODT enables the on die termination.
  • <Value> is one of the valid ODT values for the specified IOSTANDARD.
  • port_name is an input or bidirectional port connected to a differential buffer.
Related reference