PBLOCK is a read-only property attached to cells that assigned to Pblocks in the Vivado Design Suite.
A Pblock is a collection of cells, and one or more rectangular areas or regions that specify the device resources contained by the Pblock. Pblocks are used during floorplanning placement to group related logic and assign it to a region of the target device. Refer to the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906) for more information on the use of Pblocks in floorplanning your design.
Pblocks are created using the create_pblock Tcl command, and are
populated with cells using the add_cells_to_pblock command. The
following code defines a Pblock:
create_pblock Pblock_usbEngine
add_cells_to_pblock [get_pblocks Pblock_usbEngine] [get_cells -quiet [list usbEngine1]]
resize_pblock [get_pblocks Pblock_usbEngine] -add {SLICE_X8Y105:SLICE_X23Y149}
resize_pblock [get_pblocks Pblock_usbEngine] -add {DSP48_X0Y42:DSP48_X1Y59}
resize_pblock [get_pblocks Pblock_usbEngine] -add {RAMB18_X0Y42:RAMB18_X1Y59}
resize_pblock [get_pblocks Pblock_usbEngine] -add {RAMB36_X0Y21:RAMB36_X1Y29}
The first line creates the Pblock, giving it a name.
The second line assigns logic cells to the Pblock. In this case, all of the cells in the specified hierarchical module are assigned to the Pblock. Cells that are assigned to a specific Pblock are assigned the PBLOCK property.
The subsequent commands, resize_pblock, define the size of the Pblock by specifying a range of device resources that are contained inside the Pblock. A pblock has a grid of four device resource types: SLICE/CLB, DSP48, RAMB18, RAMB36. Logic that does not match one of these device types can be placed anywhere in the device. To constrain just the Block RAMs in the level of hierarchy, disable (or simply do not define) the other Pblock grids.
Refer to the Vivado Design Suite Tcl Command Reference Guide (UG835) for details on the specific Tcl commands mentioned above.
- Architecture Support
- All architectures
- Applicable Objects
- Cells (
get_cells) - Values
-
<NAME>: The property value is the name of the Pblock that the cell is assigned to. The Pblock name is defined when the Pblock is created with thecreate_pblockcommand.
Syntax
- Verilog Syntax
-
Not applicable
- VHDL Syntax
-
Not applicable
- XDC Syntax
-
The Pblock can be defined in the XDC file, or directly in the design, with the Tcl command:
create_pblock <pblock_name>XDC Example
The following code defines a Pblock:
create_pblock Pblock_usbEngine add_cells_to_pblock [get_pblocks Pblock_usbEngine] [get_cells -quiet [list usbEngine1]] resize_pblock [get_pblocks Pblock_usbEngine] -add {SLICE_X8Y105:SLICE_X23Y149} resize_pblock [get_pblocks Pblock_usbEngine] -add {DSP48_X0Y42:DSP48_X1Y59} resize_pblock [get_pblocks Pblock_usbEngine] -add {RAMB18_X0Y42:RAMB18_X1Y59} resize_pblock [get_pblocks Pblock_usbEngine] -add {RAMB36_X0Y21:RAMB36_X1Y29}
Affected Steps
- Design Floorplanning
- Place Design