The Post CRC INIT Flag property (POST_CRC_INIT_FLAG) determines whether the INIT_B pin is enabled as an output for the SEU (Single Event Upset) error signal. This feature is only supported in 7 series FPGAs. For more information refer to the 7 Series FPGAs Configuration User Guide (UG470).
The error condition is always available from the FRAME_ECC site. However, when the POST_CRC_INIT_FLAG is ENABLED, which is the default, the INIT_B pin also flags the CRC error condition when it occurs.
This property is only applicable when POST_CRC is set to ENABLE.
- Architecture Support
- 7 series FPGAs.
- Applicable Objects
- Design (
current_design): The current implemented design.
DISABLE: Disables the use of the INIT_B pin, with the FRAME_ECC site as the sole source of the CRC error signal.
ENABLE: Leaves the INIT_B pin enabled as a source of the CRC error signal (default).
- Verilog Syntax
- VHDL Syntax
- XDC Syntax
set_property POST_CRC_INIT_FLAG ENABLE | DISABLE [curent_design]
XDC Syntax Example:
set_property POST_CRC_INIT_FLAG Enable [current_design]
- Write Bitstream