The PRE_EMPHASIS property is used to improve signal integrity of high-frequency signals that suffer high-frequency losses through the transmission line. The transmitter pre-emphasis (PRE_EMPHASIS) feature allows pre-emphasis on the signal drivers for certain I/O standards.
Ideal signals perform a logic transition within the symbol interval of the frequency. However, lossy transmission lines can expand beyond the symbol interval. Pre-Emphasis provides a voltage gain at the transitions to account for transmission-line losses. In the frequency domain, pre-emphasis boosts the high-frequency energy on every transition in the data stream.
The pre-emphasis selection is also a key to the signal integrity at the receiver. Pre-emphasis increases the signal edge rate, which also increases the crosstalk on neighboring signals.
Because the impact of pre-emphasis on crosstalk and signal discontinuity is dependent on the transmission line characteristics, simulation is required to ensure the impact is minimal. Over emphasis of the signal can further degrade the signal quality instead of improving it.
- Architecture Support
- Applicable Objects
- Ports (
- The allowed values for the PRE_EMPHASIS attribute are:
RDRV_240: Enable pre-emphasis. When enabled, the ENABLE_PRE_EMPHASIS property on the TX_BITSLICE must also be set to TRUE.
RDRV_NONE: Do not enable transmitter pre-emphasis (default).
- Verilog Syntax
- VHDL Syntax
- XDC Syntax
The PRE_EMPHASIS attribute uses the following syntax in the XDC file:
set_property PRE_EMPHASIS value [get_ports port_name]
set_propertyPRE_EMPHASIS enables pre-emphasis at the transmitter.
port_nameis an output or bidirectional port connected to a differential output buffer.