The RAM_DECOMP property instructs the tool to infer RTL RAMs that are too large to fit in a single block RAM primitive to use a power efficient configuration, rather than a timing efficient solution.
For example, a RAM specified as 2K x 36 would often be configured as two 2K x 18 block RAMs arranged side by side. This configuration yields the best timing results. However, by setting the RAM_DECOMP property, the RAM would instead be configured as 2 1K x 36 block RAMs. This configuration is more power-efficient because during a read or write, only the RAM with the address being used is active. This configuration is less timing efficient though, because Vivado synthesis must then use address decoding. This attribute can be set in either RTL or XDC.
- Architecture Support
- All architectures.
- Applicable Objects
- Cells (
get_cells): Apply to RAM cells. - Values
-
power: Configure RAM in a power efficient way, rather than timing efficient.Important: To restore the default synthesis behavior, you must remove the RAM_DECOMP property as there is no default setting.
Syntax
- Verilog Syntax
-
(* ram_decomp = “power” *) reg [data_size-1:0] myram [2**addr_size-1:0]; - VHDL Syntax
-
Declare the VHDL attribute as follows:
attribute ram_decomp : string; attribute ram_decomp of myram : signal is “power”; - XDC Syntax
-
set_property ram_decomp power [get_cells myram]
Affected Steps
- Synthesis