RLOC_ORIGIN - 2023.2 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
Release Date
2023.2 English

The RLOC_ORIGIN property provides an absolute location, or LOC, for the relatively placed macro (RPM) in the RTL design. For more information on defining RPMs, and using the RLOC_ORIGIN property, refer to the Vivado Design Suite User Guide: Using Constraints (UG903).

RPMs are defined by assigning design elements to a set using the H_SET, HU_SET, or U_SET properties in the RTL design. The design elements are then assigned a relative placement to one another using the RLOC property. You can define the relative placement of any element within the set relative to other elements in the set, regardless of the eventual placement of the entire group onto the target device.

Having defined the elements of an RPM, and their relative placement, the RLOC_ORIGIN property lets you define the absolute placement of the RPM onto the target device. The RLOC_ORIGIN property is converted into LOC constraint during synthesis.

In the Vivado Design Suite, the RLOC_ORIGIN property defines the lower-left corner of the RPM. This is most often the design element whose RLOC property is X0Y0. Each remaining cell in the RPM set is placed on the target device using its relative location (RLOC) as an offset from the group origin (RLOC_ORIGIN).

Architecture Support

All architectures.

Applicable Objects

Instances within the RTL source file.


The Relative Location constraint is specified using a SLICE-based XY coordinate system.



  • m is an integer representing the absolute X coordinate on the target device of the lower-left corner of the RPM.
  • n is an integer representing the absolute Y coordinate on the target device of the lower-left corner of the RPM.


Verilog Syntax

The RLOC_ORIGIN property is a Verilog attribute defining the absolute placement of an RPM on the target device. Place the Verilog attribute immediately before the instantiation of a logic element.

(* RLOC_ORIGIN = "XmYn", HU_SET = "h0" *) FD sr0 (.C(clk), .D(sr_1n), .Q(sr_0));

Verilog Example:

The following top-level Verilog module defines the RLOC_ORIGIN property for the ffs modules in the design.

module top (
input	clk, input	d, output q

wire	c1, c2;

(* RLOC_ORIGIN = "X1Y1", KEEP_HIERARCHY = "YES" *) ffs u0 (clk, d, c1); 
(* RLOC_ORIGIN = "X3Y3", KEEP_HIERARCHY = "YES" *) ffs u1 (clk, c1, c2); 
(* RLOC_ORIGIN = "X5Y5", KEEP_HIERARCHY = "YES" *) ffs u2 (clk, c2, q);

endmodule // top
VHDL Syntax

Declare the VHDL constraint as follows:

attribute RLOC_ORIGIN: string;

Specify the VHDL constraint as follows:

attribute RLOC_ORIGIN of {component_name | entity_name | label_name} :
{component|entity|label} is “XmYn”;


  • {component_name | entity_name | label_name} is a choice of one design element.
  • {component | entity | label} is the instance ID of the design element.
  • XmYn defines the RLOC_ORIGIN value for the specified design element.
XDC Syntax
The RLOC_ORIGIN property translates to the LOC property in the synthesized design. You can specify the LOC property of RPMs by placing one of the elements of the RPM onto the target device. The other elements of the RPM will be placed relative to that location, and assigned to LOC property.

Affected Steps

  • Logical to Physical Mapping
  • Place Design
  • Synthesis