SYNTH_CHECKPOINT_MODE - 2023.2 English

When generating the output products for a Vivado IP integrator block design file (.bd), you can chose how the block design is synthesized in coordination with the top-level design. Refer to this link in Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) for more information. Using the SYNTH_CHECKPOINT_MODE you can specify that the block design will be synthesized as part of the top-level design, during global synthesis. Do this by setting SYNTH_CHECKPOINT_MODE to NONE, disabling the generation of the OOC synthesis checkpoint for the block design.

Important: When SYNTH_CHECKPOINT_MODE is set to NONE, the Vivado tool automatically sets the GENERATE_SYNTH_CHECKPOINT property to FALSE, or 0, to disable the OOC flow and the generation of the synthesized DCP output product for BD files.

You can also choose that the block design should be synthesized out-of-context (OOC) from the rest of the design, by setting the SYNTH_CHECKPOINT_MODE property to either SINGULAR or HIERARCHICAL:

SINGULAR specifies that the block design will be synthesized as a single unit, and written to a single DCP. In the Vivado IDE this option is referred to as Out-of-context per Block Design.
HIERARCHICAL specifies that all IP used in the block design will be synthesized, and written to separate DCP files for each IP. In the Vivado IDE this option is referred to as Out-of-context per IP. This is the default mode.

This property will become read-only if the IP is locked for any reason. In this case, you can run Reports > Report IP Status in the Vivado IDE, or run the report_ip_status Tcl command to see why the IP is locked. You will not be able to generate the DCP without first updating the IP to the latest version in the Vivado IP catalog. Refer to this link in the Vivado Design Suite User Guide: Designing with IP (UG896) for more information.

Architecture Support

All architectures.

Applicable Objects

Block Design Files (BD)
(get_files)

Values

None: Indicates that the block design should be synthesized along with the rest of the design. This is known as global synthesis.
Singular: Indicates that the entire block design should be synthesized as an out-of-context block.
Hierarchical: Indicates that each IP used in the block design should be synthesized separately. That is each IP should be synthesized out-of-context to maximize the use of the synthesis cache whenever re-synthesis is needed. This is the default mode.

Syntax

Verilog Syntax

Not applicable

VHDL Syntax

Not applicable

XDC Syntax

The following command examples show setting the various SYNTH_CHECKPOINT_MODE values, and using the generate_targets Tcl command to create the output.

Global Synthesis:

set_property SYNTH_CHECKPOINT_MODE NONE [get_files <filename>.bd] generate_target all [get_files <filename>.bd]

OOC per IP:

set_property SYNTH_CHECKPOINT_MODE HIERARCHICAL [get_files <filename>.bd] generate_target all [get_files <filename>.bd]

OOC per block design:

set_property SYNTH_CHECKPOINT_MODE SINGULAR [get_files <filename>.bd] generate_target all [get_files <filename>.bd]

Where <filename> is the filename of a block design (BD).

XDC Syntax Example:

set_property SYNTH_CHECKPOINT_MODE SINGULAR [get_files *.bd] generate_target all [get_files *.bd]

Affected Steps

Synthesis
Implementation