For UltraScale architecture, the UNAVAILABLE_DURING_CALIBRATION property disables a DRC error message to report that BITSLICE0 is not available during the built-in self-calibration (BISC) process.
IDELAY/ODELAY and RX_BITSLICE/TX_BITSLICE/RXTX_BITSLICE support TIME mode for DELAY_FORMAT that provides more precise delays by continuously adjusting the alignment. When TIME mode is used for IDELAY/ODELAY and native primitives, BITSLICE_0 is used during the BISC process. Component logic connected to BITSLICE_0 might not be available during the BISC process. In this case, the Vivado tool will issue a DRC violation to indicate that input routing and logic associated with BITSLICE_0 within a nibble will be unavailable during the BISC operation. Refer to the DELAY_FORMAT attribute in the UltraScale Architecture SelectIO Resources User Guide (UG571) for more information.
If these restrictions do not affect a design, the DRC can be disabled with the UNAVAILABLE_DURING_CALIBRATION property.
- Architecture Support
- UltraScale architecture.
- Applicable Objects
- Ports (
- Disable reporting of the DRC error message related to the BISC process.
- Do not disable the reporting of the DRC error message (default).
- Verilog Syntax
- VHDL Syntax
- XDC Syntax
set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports <port_name>]