AXI4-Lite Interface - 1.0 English

AXI4-Stream Video IP and System Design Guide (UG934)

Document ID

UG934

Release Date

2022-11-16

Version

1.0 English

Many video applications have an embedded processor that can dynamically monitor and control processing parameters within IP cores. The AXI4-Lite interface provides a standardized API across which core functionality can be controlled and monitored. Layers of the API consist of a memory-mapped interface with programmable registers, a low level driver to identify physical memory locations, and higher level driver functions to control multiple registers or complex processes. The proposed standard set of memory mapped registers is described in Table: Standard Video IP Registers .

Table 3-2: Standard Video IP Registers
Offset	Function	Default	Access	Bit-field Definitions
0x0000	CONTROL	0	R/W	Bit 0: SW_ENABLE Bit 1: REG_UPDATE Bit 4: BYPASS (Optional. See Core Bypass Option .) Bit 5: TEST_PATTERN (Optional. See Built in Test-Pattern Generator .) Bit 31: SW_RESET (1: reset)
0x0004	STATUS	0	R/W	Bit 0: Frame processing Started Bit 1: Frame Processing Complete Bits 2-15: Core specific Status Flags Bit 16: Slave0 error Bit 17: Slave1 error (Optional) Bit 18: Slave2 error (Optional) Bit 19: Slave3 error (Optional)
0x0008	ERROR	0	R/W	Bit 0: Slave0 EOL early Bit 1: Slave0 EOL late Bit 2: Slave0 SOF early Bit 3: Slave0 SOF late Bit 4: Slave1 EOL early (Optional) Bit 5: Slave1 EOL late (Optional) Bit 6: Slave1 SOF early (Optional) Bit 7: Slave1 SOF late (Optional)
0x000C	IRQ_ENABLE	0	R/W	Bit 0-31: Interrupt enable bits corresponding to STATUS conditions
0x0010	VERSION		R	31-16: Core version in 4bits. 4bits format. 0-15: CRC generated by CORE Generator (Optional. See Version Register .)
0x0014	SYSDEBUG0	0	R	Frame Throughput monitor (Optional)
0x0018	SYSDEBUG1	0	R	Line Throughput monitor (Optional)
0x001C	SYSDEBUG2	0	R	Pixel Throughput monitor (Optional)
0x0020	Timing Register Set 0		Application Dependent	See Timing Representation .
0x005C	Timing Register Set 0		Application Dependent	See Timing Representation .
0x0060	Timing Register Set 1		Application Dependent	Optional for IP using multiple interfaces with different Encoding or Timing.
0x009C	Timing Register Set 1		Application Dependent
0x00A0 - 0x00FC	Reserved
0x0100	Core Specific Registers		Application Dependent	Defined in Core Data Sheets
0x3FFC	Core Specific Registers		Application Dependent	Defined in Core Data Sheets

For more information on optional debugging, see Debugging Features .