Basic Video System with Interlace Content - 1.0 English

AXI4-Stream Video IP and System Design Guide (UG934)

Document ID
UG934
Release Date
2022-11-16
Version
1.0 English

This Figure shows the interfaces on Video In to AXI4-Stream, AXI4-Stream to Video Out, and VTC cores to support the video field ID with the interlace-related signals highlighted in red.

Figure 2-10: Video System with Interlaced Content Using AXI4-Stream Bridges

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Most video processing cores are field-agnostic, and not aware of whether the picture being processed is an odd or even frame, or a progressive field. Therefore, interlace has no impact on these cores. The Video In to AXI4-Stream core has a frame ID output, fid , timed to the native video bus. This signal can be used as needed in the system. The only cores that use this fid bit are the AXI4-Stream to Video Out.

AXI4-Stream to Video Out core aligns the axi_field_id signal with the field_id signal generated by Video Timing Controller module. You can directly connect the field_id signal to AXI4-Stream to Video Out core bypassing the Video processing cores as shown in Figure This Figure only when latency of the processing core is less than one Video frame. If the latency is more than one video frame, respective video processing cores should delay the field id signal accordingly.

On the Video In to AXI4-Stream core, the fid bit changes coincident with SOF and remains constant throughout the remainder of the field. On the AXI4-Stream to Video Out core, the fid bit is sampled coincident with SOF in This Figure . Therefore, the Video In to AXI4-Stream can provide the field bit directly to the AXI4-Stream to Video Out core if no intervening frame buffer exists. When a deinterlacer or frame buffer is used, a similar scheme can be employed: generate the field ID coincident with the start of the field, and on the receiving side sample the field ID coincident with the first received pixel.

Figure 2-11: AXI4-Stream Data Timing Diagram with field ID Signal

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Frame buffer read/Write and Video Deinterlacer cores. The AXI4-Stream to Video Out core has a field ID input ( fid ), sampled in time with the AXI4-Stream input bus. This fid bit must be asserted by the upstream source of AXI4-Stream video. For systems without a frame buffer or deinterlacing, the field ID input originates from the Video In core, as shown in This Figure .

Figure 2-12: Video System with Interlaced Content Using Frame Buffer Write/Read

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For systems with a frame buffer, the field ID input can come from any core containing a frame buffer. The field ID from the Video In to AXI4-Stream core can be used by the frame buffer if necessary, shown in This Figure .

Note: In This Figure , the AXI4-Stream to Video Out core is operating in slave mode.