The input interface core automatically detects if timing signals ( VSync , HSync , VBlank , HBlank ) are inverted. Periodic sync pulses are defined as Active Low if the low portion of the signal is shorter than the high portion (signal pulses low). Bits 0 and 1 of timing variable POLARITY correspond to VSync and HSync respectively, and should be set to 1 when Active Low sync pulses are detected or to 0 when Active Low sync pulses are not detected
Periodic Blank signals are defined Active Low if the low portion of the signal is shorter than the high portion because an active area is expected to be longer than the blanked area. Bits 2 and 3 of timing variable POLARITY correspond to VBlank and HBlank respectively, and should be set to 1 when active low blank signals are detected or 0 when Active Low blank signals are not detected.