Even if sufficiently deep line buffers (FIFOs) are present on the output of processing cores, bubbles can form if buffers under-run. This can happen when a core master interface asserts its VALID output immediately when the core output FIFO is not empty. In this case, data percolates through a processing pipeline rapidly and trigger the output interface to start output timing generation, after which output pixels have to be supplied consistently. Now, if any of the cores cannot sustain the uninterrupted data rate and have to deassert its VALID output, processing bubbles form, which eventually cause a buffer under-run at the output interface core and break the output data–sync alignment.
1. Core A and Core B ran out of valid samples.
This Figure presents an example scenario when processing cores A and B run out of valid samples mid-frame, so when the output interface asserts its ready output to start a new line, samples must be retrieved from external memory and must be processed by Core A and Core B, causing significant delay, which can break the sync - data alignment at the output interface.
To avoid processing bubbles, cores should not assert the VALID signal on the output interfaces until internal FIFOs are almost full and keep VALID asserted until output FIFOs and internal pipeline stages are empty.
The READY output should be driven in a greedy fashion; asserted unless all pipeline stages are full, internal FIFOs are almost full, and the master interface READY is sampled low, as described in READY – VALID Propagation , or internal pipelines need to be flushed as described in Flushing Pipelined Cores . This behavior ensures processing efficiency and proper flushing of pipelines and processing systems at line and frame ends.