Control Register - 1.0 English

AXI4-Stream Video IP and System Design Guide (UG934)

Document ID
UG934
Release Date
2022-11-16
Version
1.0 English

The SW_ENABLE flag, located on bit 0 of the CONTROL register, allows the core to be dynamically enabled or disabled. Disabling the core from software has similar effects as deasserting ACLKEN . When disabled, the core AXI4-Lite decoding units remain active to facilitate re-enabling the core. The default value of Software Enable is 1 (enabled).

Flags of the CONTROL register are not buffered, which means changes take effect immediately. The application or higher-level driver functions need to deassert these flags to re-enable status/error acquisition.