Core Bypass Option - 1.0 English

AXI4-Stream Video IP and System Design Guide (UG934)

Document ID
UG934
Release Date
2022-11-16
Version
1.0 English

If conceptually possible, video processing IP cores should facilitate an optional straight through connection between input (AXI4-Stream slave) and output (AXI4-Stream master) by-passing any processing functionality.

Use Flag BYPASS , located on bit 4 of the CONTROL register, to turn bypassing on (1) or off. For single-clock-domain IP cores, this switch can control multiplexers in the AXI4-Stream path. For applications where the input and output AXI4-Stream interfaces are in different clock domains, the bypass multiplexers select between a clock-domain crossing FIFO implemented using distributed memory and the actual video processing core.