A frame period for progressive video is defined by the number of video clock cycles between Vsync pulses. Similarly, a field period for interlaced video is defined by the number of video clock cycles between Vertical Sync pulses.
The field periods for even (F0) and odd (F1) fields can differ. A frame period for interlaced video is defined by the sum of two subsequent (odd + even) field periods. The frame periods for both interlaced and progressive video is expected to be constant for any given video format.
The intervals when both HBlank and VBlank are inactive mark the active video area of the frame, where pixel data is considered valid and should be translated from a periodic standard such as DVI to AXI4-Stream.
The frame period contains blank and active areas and can be visualized as a set of rectangles, as seen in This Figure . In the top-left corner of the frame, pixel index 0 (scan line index 0) is designated to be the first active pixel on the first complete active line.
The total number of scan lines per frame is defined as the number of scan-lines per frame, or VSIZE . The timing variable VSIZE reflects the total number of active and blank lines per frame. The index of the last scan line in a frame is VSIZE -1.
The number of video clock cycles between the HBlank pulses is expected to be equal to the number of video clock cycles between the HSync pulses in each field. The timing variable HSIZE reflects the total number of active and blank pixels per scan line. The index of the last pixel in scan lines is HSIZE -1.
The Xilinx Video Timing Controller IP works with complete scan lines, so the total number of video clock cycles in a frame period is expected to be an integer multiple of the total number of pixels per scan line ( HSIZE * VSIZE ).
For progressive video, the period between the VBlank pulses is expected to have the same number of video clock cycles as the period between the VSync pulses. For interlaced video, the number of total scan lines in even and odd fields can differ. Therefore, two sets of timing registers (F0 for even fields and F1 for odd fields) keep track of timing variables for interlaced video fields.
For progressive video, only the F0 bank of timing registers are used.
The falling and rising edges of VBlank might not coincide with the falling edge of HBlank , which could be visualized as VBlank falling on a pixel position other than 0 in a scan line ( This Figure ). Also, the phase difference between VBlank and HBlank can change between even and odd fields. This phase difference between the falling and rising edges of VBlank is captured in the nibbles of the registers F0_VBLANK_H and F1_VBLANK_H .
The phase relationships of the VSync and HSync signals can be arbitrary in relationship to the first active pixel, the origin of the V/H coordinate system ( This Figure ), and might be different between even and odd fields. Nibbles in registers F0_VSYNC_V and F0_VSYNC_H capture the horizontal and vertical positions of falling and rising edges of VSYNC for even fields. Similarly, nibbles in registers F1_VSYNC_V and F1_VSYNC_H capture the horizontal and vertical positions of falling and rising edges of VSYNC for odd fields.
The scan line index where VBlank transitions high1 ( VBlank start) marks the vertical end of the active area and the start of the vertical blank area. The pixel index where HBlank transitions high1 ( HBlank start) marks the horizontal end of the active area, and the start of the horizontal blank area.
Nibbles of timing registers ACTIVE_SIZE denote the vertical (number of scan lines), and horizontal sizes (number of pixels) in the active area.